MPQ2362

— DUAL 2A, 23V, 380kHz STEP-DOWN CONVERTER, AEC-Q100 QUALIFIED

MPQ2362 Rev. 1.0

www.MonolithicPower.com

12

5/24/2016

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ESR

ESR

R

2

C

2

1

f









In this case (as shown in Figure 2), a third pole

set by the compensation capacitor (C6) and the

compensation

resistor

(R3)

is

used

to

compensate the effect of the ESR zero on the

loop gain. This pole is located at:

3

R

6

C

2

1

f

3

P









The goal of compensation design is to shape

the converter transfer function to get a desired

loop gain. The system crossover frequency

where the feedback loop has the unity gain is

important.

Lower crossover frequencies result in slower

line and load transient responses, while higher

crossover frequencies could cause system

unstable. A good rule of thumb is to set the

crossover frequency to below one-tenth of the

switching

frequency.

To

optimize

the

compensation components for conditions not

listed in Table 2, the following procedure can be

used:

1. Choose the compensation resistor (R3) to set

the desired crossover frequency. Determine the

R3 value by the following equation:

FB

OUT

CS

EA

C

V

V

G

G

f

2

C

2

3

R













which is typically less than one tenth of the

switching frequency.

2. Choose the compensation capacitor (C3) to

achieve

the

desired

phase

margin.

For

applications with typical inductor values, setting

of the crossover frequency provides sufficient

phase margin. Determine the C3 value by the

following equation:

C

f

3

R

2

4

3

C









Where R3 is the compensation resistor value.

3. Determine if the second compensation

capacitor (C6) is required. It is required if the

ESR zero of the output capacitor is located at

less than half of the switching frequency, or the

following relationship is valid:

2

f

R

2

C

2

1

S

ESR









If this is the case, then add the second

at the location of the ESR zero. Determine the

C6 value by the equation:

3

R

R

2

C

6

C

ESR





Frequency Synchronization

Each channel of the MPQ2362 can be driven

with an external clock of up to 1.2MHz, high

frequency synchronization and low VIN can not

be achieved the same switching time. The

rising edge of the external clock resets the

internal clock, and the amplitude of the external

clock must be greater than 2.7V.

External Bootstrap Diode

An external bootstrap diode may enhance the

efficiency

of

the

regulator,

the

applicable

conditions of external BST diode are:





Duty cycle is high: D=

IN

OUT

V

V

>65%

In these cases, an external BST diode is

recommended from the output of the voltage

regulator to BST pin, as shown in Figure2

Figure 2

—Add Optional External Bootstrap

Diode to Enhance Efficiency

The recommended external BST diode is

IN4148, and the BST cap is 0.1~1µF.