The Smart Timing Choice

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The Smart Timing Choice



SiT3921

Digitally Controlled Differential Oscillator (DCXO)

Rev. 1.1

Page 3 of 12

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Default Startup Condition

The SiT3921 starts up at its factory programmed frequency and settings. The control register values are initialized all zeros,

effectively setting the frequency to the middle of the control range.

Frequency Control Protocol Description

The device includes two DCXO registers; writing to these registers controls the output frequency. Data for each register is writ-

ten to the device using a data frame.

Data Frame Format

Each frame consists of 40 bits. A frame has 3 parts:

- The header, 16 bit

- Register address, 8 bit

- The data word (represented as 2's complement numbers), 16 bit.

Bits are sent MSB first.

Frames are sent LS word first in mode 2.

The header allows the devices to recognize that the master is initiating communication. The header includes the device

address, which is factory programmable. The valid header is 0xFAIA, where "I" can be a hex digits from 0 to F. If not specified

at the order time, it will be defaulted to zero. In this document in all examples and text, the device address is considered to be

zero (default).

Frequency Control Mode 1

In this resolution mode, only one frame per frequency update is

required, and the output frequency is updated at the end of each

frame. The length of the frequency control data is 16 bits, and is writ-

ten to the device as shown below:

Frequency Control Mode 2

In this mode, two frames per frequency update are required, and fre-

quency is only updated at the end of the second frame. The fre-

quency control value in this mode is 23 bits. This value is written to

the device in two frames as follows:

Figure 1. Frequency Control Mode 1

Figure 2. Frequency Control Mode 2

Resolution and Update Rate for Mode 1

Resolution and Update Rate for Mode 2

Pull Range (ppm)

Step Resolution (ppb)

Max Update Rate

(Updates Per Second)

Pull Range (ppm)

Step Resolution (ppb)

Max Update Rate

(Updates Per Second)

±25

125 K

±25

1

12.5 K

±50

1.5

25 K

±50

1

12.5 K

±100

325 K

±100

1

12.5 K

±200

625 K

±200

1

12.5 K

±400

12

25 K

±400

1

12.5 K

±800

25

25 K

±800

1

12.5 K

±1600

49

25 K

±1600

1

12.5 K

H e ader

0 x F A 0A , (16 bits )

F reque nc y C ontro l V a lue

(1 6 b its )

R e g A d dres s

0x 06 or 0 x 0 7

(8 b its )

0

15 1 6

23 24

3 9