The Smart Timing Choice



The Smart Timing Choice



SiT5000

Standard Frequency MEMS (VC)TCXO

Rev. 1.0

Page 3 of 7

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Timing Diagram

Phase Noise Plot

50% Vdd

Vdd

ST Voltage

CLK Output

T_resume

T_resume: Time to resume from ST

90% Vdd, 2.5/2,8/3.3V devices

95% Vdd, 1.8V devices

Vdd

Pin 4 Voltage

CLK Output

T_start

T_start: Time to start from power-off

(ST/OE Mode)

(ST Mode Only)

10

3

10

4

10

5

10

6

-170

-160

-150

-140

-130

-120

-110

-100

Frequency Offset (Hz)

Phase Noise, 10MHz carrier, 3.3V, LVCMOS output, TCXO

Integrated random phase jitter (RMS, 12kHz-5MHz): 0.52ps