MP8848 – 6A, HIGHLY EFFICIENT, SYNC, STEP-DOWN SWITCHER WITH I

MP8848 Rev. 1.0

www.MonolithicPower.com

18

2/16/2017

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PG Configuration

The MP8848 has an option to use the

PG_LOHI function. This function can be written

in the PG_LOHI bit (Reg02 Syscntlreg1 [D2]).

The default value is 1, where PG senses both a

positive and negative excursion of Vo from the

reference. If writing this bit to 0, PG only senses

a negative voltage excursion of Vo from the

reference.

Input Over-Voltage Protection (OVP)

The MP8848 has an option to use the

VIN_OVP function. This function can be written

in the VIN_OVP bit (Reg02 Syscntlreg1 [D1]).

The default value is 0, where the VIN_OVP

function is enabled. When VIN is higher than

6.3V, the converter is disabled. After VIN

recovers to 6.2V, the converter restarts. If the

VIN_OVP bit is set to 1, VIN OVP is disabled.

The converter will not stop, even if VIN exceeds

its safe range.

Forced Continuous Conduction Mode (CCM)

The

MP8848

has

auto-pulse-frequency

modulation (PFM) mode and forced continuous

conduction mode (CCM). This function can be

written in the Mode bit (Reg02 Syscntlreg1

[D0]). The default value is 0, where auto-PFM

mode is selected. Considering a smaller Vo

ripple and regulation for a full load range, forced

CCM is recommended. Set this bit to 1 to

disable PFM mode.

Output Discharge

The MP8848 has an output discharge function.

Writing the Out-dis bit (Reg03 SysCntlreg2 [D4])

can change the output discharge mode. The

default value is 1. Discharge the internal Vo

resistance when EN is low. Writing D4 = 1 can

enable the function, and then the output voltage

can be discharged by the internal pull-down

resistance.

Output Voltage Transition Slew Rate

When the output voltage switches from low to

high or from high to low, the transition slew rate

can differ. There are two possible values for

selection. Through writing the Slew Rate bits

(Reg03 Syscntlreg2 D2), the transition slew rate

can be set at one possible value based on the

application. The internal reference follows the

set slew rate, but the output voltage slew rate

does not always follow the internal reference.

Considering the output capacitor and inductor,

the actual output voltage slew rate should be a

little slower.

AVIN Multi-Use

The MP8848’s AVIN pin has multi-usage. When

the P3 Enable bit (Reg03 SysCntlreg2 D1) is 0,

AVIN is an internal analog supply. When the P3

Control bit (Reg03 sysCntlrge2 D1) is 1, the P3

voltage is controlled by the P3 Set bit (Reg03

sysCntlrge2 D0). The P3 voltage is high if D0 =

0; otherwise, the P3 voltage is low (see Table

3).

Table 3: AVIN Multi-Use

D1

D0

AVIN

0

0

Internal analog supply

0

1

1

0

Forced to 1

1

1

Forced to 0

I

register can hold on after EN changes low. The

updated register can be held for later

application conditions, even if the external EN

pulls low.