MP3221 datasheet(12/14 Pages) MPS

12 / 14 page

MP3221

–2.7A, 1.2MHZ, HIGH-EFFICIENCY STEP UP CONVERTER WITH INPUT DISCONNECT

MP3221 Rev. 1.0

www.MonolithicPower.com

9/23/2013

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

should be greater than 1.5 times of the input

voltage.

The

maximum

current

through

the

power

MOSFET happens when the input voltage is

minimum and the output power is maximum.

The maximum Average current is the input

current. The ID(max) should be greater than 1.5

times the input current.

The on resistance of the MOSFET determines

the conduction loss. It is smaller, it is better.

The Qg of PMOS should be well designed to

avoid the triggering of SCP protection during

start-up. Since VGATE is pulled down with 115μA

through the Fault pin, the SCP function is

enabled after VGATE drops to VIN-1.8V. With

higher Qg, the time to pull VGATE from VIN to VIN-

1.8V is longer, and output voltage can be

charged to higher voltage. If Qg is low, VGATE will

be pulled down quickly, and feedback VFB is still

lower than 150mV when VGATE drops to VIN-1.8V,

then SCP function may be triggered and the

start-up will fail.

A 3.3nF cap between gate-to-source of PMOS is

recommended if VOUT can not rise up before

VFAULT drops to VIN -1.8V due to large output cap.

PCB Layout Considerations

Layout is important, especially for switching

power supplies with high switching frequencies;

poor layout results in reduced performance, EMI

problems,

resistive

loss,

and

even

system

instability. Following the rules below can help

ensure a stable layout design:

1. All components must be placed as close to

the IC as possible. Keep the path between L1,

D1, COUT, and IC-GND extremely short for

minimal noise and ringing.

2. CIN must be placed close to the IN pin for best

decoupling.

3. All feedback components must be kept close

to the FB pin to prevent noise injection on the

FB pin trace.

4. The ground return of CIN and COUT should be

tied close to the GND pin.

Top Layer

Via

Fault

Vin

GND

MP 3221

Bottom Layer

Vout

GND

Vin

Figure 2: Layout

Notes:

Refer to SCH on page 1.

Design example

Below

design

example

following

the

application guidelines for the following

Specifications:

Table 1: Design Example

VIN

2.5V-4.8V

VOUT

FSW

1.2MHz

The typical application circuit for VOUT = 5V in

Figure

shows

the

detailed

application

schematic, and is the basis for the typical

performance and circuit waveforms. For more

detailed device applications, please refer to the

related Evaluation Board Datasheets.

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