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MP4054 Datasheet(PDF) 12 Page - Monolithic Power Systems |
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MP4054 Datasheet(HTML) 12 Page - Monolithic Power Systems |
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12 / 19 page ![]() MP4054 – NON-ISOLATED OFFLINE LED CONTROLLER WITH ACTIVE PFC MP4054 Rev. 1.0 www.MonolithicPower.com 12 12/25/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. VREF—The feedback reference voltage (typical 0.413V); RS—The sensing resistor connected between the MOSFET source and GND. In high-side solution (including both Buck and Buck-boost), the proprietary direct-current control method allows the MP4054 to control the LED current accurately. The mean value of the output LED current is calculated approximately as: REF o FB V I R RFB—The sensing resistor connected between the FB RC filter and GND in high- side solution Power-Factor Correction (PFC) MULT is connected to a pull-up resistor from the rectified-instantaneous-line voltage; the multiplier output is sinusoidal. This signal sets the sinusoidal inductor peak current. This achieves a high power factor (PF). Inductor current Multiplier output Figure 4: Power-Factor Correction The maximum output voltage of the multiplier is clamped to 2.0V, setting the cycle-by-cycle current limit. VCC Under-Voltage Lockout (UVLO) When the VCC voltage drops below the UVLO threshold 9.5V, the IC stops switching and shuts down; the operating current is very low under this condition. VCC is then charged by the external resistor from the AC line. Figure 5 shows the typical waveform of UVLO. Figure 5: VCC Under-Voltage Lockout Auto Starter The MP4054 integrates an auto-restart that begins timing when the MOSFET turns off. If ZCD fails to send a turn-on signal after 190µs, a turn-on signal is initiated. This avoids an unnecessary IC shut down if ZCD misses detection. Minimum Off Time The MP4054 operates with variable switching frequency. The frequency changes with the input instantaneous line voltage. To limit the maximum frequency and enhance EMI performance, the chip employs an internal minimum OFF-time of 5.5µs. Leading-Edge Blanking (LEB) Internal leading-edge-blanking (LEB) is employed to prevent a switching pulse from terminating prematurely due to parasitic capacitance discharging when the MOSFET turns on. During the blanking time, the path from CS/ZCD to the current comparator input is blocked. Figure 6 shows the leading-edge blanking time. The LEB time of OCP detection is relatively short at 280ns. t LEB =400 n s V CS t Figure 6: Leading-Edge Blanking |
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