MP4054 – NON-ISOLATED OFFLINE LED CONTROLLER WITH ACTIVE PFC

MP4054 Rev. 1.0

www.MonolithicPower.com

13

12/25/2014

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Output Over-Voltage Protection (OVP)

Output

over-voltage

protection

prevents

component

damage

from

over-voltage

conditions.

The auxiliary winding’s positive

plateau voltage is proportional to the output

voltage; the OVP uses the auxiliary-winding

voltage instead of directly monitoring the output

voltage.

Figure 7 shows the OVP circuit. Once the ZCD

voltage is higher than 5.1V and exceeds the

OVP blanking time (during the gate turn-off

interval), the OVP signal is latched, turning the

gate driver off. When VCC drops below UVLO,

the IC restarts.

The output OVP setting point is calculated as:







AUX

ZCD2

OUT _ OVP

L

ZCD1

ZCD2

NR

V5.1V

NR

R

output

over-voltage

protection point;

R1

Gate

CS/ZCD

5.1V

+

-

Latch

OVP

Blanking time

Gate_OFF

Figure 7: OVP Sampling Unit

To prevent a voltage spike from an OVP mis-

A current-limit resistor between the output of

the auxiliary winding and the ZCD resistor

divider also works as a suppresser to avoid an

OVP mis-trigger.

0V

Sampling Here

t

LEB_OV P

Figure 8: ZCD Voltage and OVP Sampler

Output Short-Circuit Protection (SCP)

If an output short occurs, ZCD cannot detect

the zero-current-crossing signal, so the 190μs

auto-restart timer triggers the MOSFET’s turn-

on signal. The switching frequency of the power

circuit drops to about 5kHz and the output

current is limited to its nominal current. The

auxiliary-winding voltage drops to follow the

output voltage, VCC drops to less than the

UVLO threshold, and then the system restarts.

This sequence limits both the output power and

IC temperature if an output short occurs.

Over-Current Protection (OCP)

The over-current protection prevents device

damage from excessive current, such as a

inductor winding short circuit. If the CS/ZCD

voltage rises to 2.46V during the gate turn-on

interval (see Figure 9), the over-current

protection signal is latched, turning the gate

driver off. When VCC drops below UVLO, the

IC restarts.

Figure 9: OCP Sampling Unit