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MP8758HGL Datasheet(PDF) 14 Page - Monolithic Power Systems |
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MP8758HGL Datasheet(HTML) 14 Page - Monolithic Power Systems |
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14 / 23 page ![]() MP8758H–22V, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER MP8758H Rev.1.0 www.MonolithicPower.com 14 10/13/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. Operating with External Ramp Compensation Usually, the MP8758H is able to support ceramic output capacitors without an external ramp. In some cases, the internal ramp may not be enough to stabilize the system, and external ramp compensation is needed. Please refer to the Application Information section on page 17 for design steps with external ramp compensation. R1 R2 Ceramic SW FB Vo L R4 C4 IR4 IC4 I FB R8 Figure 7: Simplified Circuit in PWM Mode with External Ramp Compensation Figure 7 shows a simplified external ramp compensation (R4 and C4) for PWM mode. Chose R1, R2, R8, and C4 of the external ramp to meet the condition shown in Equation (3) and Equation (4): 12 8 SW 4 1 2 RR 11 R 2F C 5 R R ⎛⎞ × <× + ⎜⎟ π× × + ⎝⎠ (3) R4 C4 FB C4 II I I =+ ≈ (4) VRAMP on VFB can then be estimated with Equation (5): IN OUT 12 RAMP ON 44 1 2 8 VV R//R VT RC R // R R − =× × ×+ (5) The downward slope of the VFB ripple can be estimated with Equation (6): − − == × OUT RAMP SLOPE1 off 4 4 V V V TR C (6) If there is instability in PWM mode, either R4 or C4 can be reduced. If C4 cannot be reduced further due to limitation from Equation (3), then only R4 can be reduced. For stable PWM operation, estimate Vslope1 with Equation (7): SW ON -3 ESR OUT slope1 OUT OUT SW on TT +-R C Io 10 0.7 π 2 -V V + 2L C T -T × × ≥ ×× (7) Where Io is the load current. In skip mode, the downward slope of the VFB ripple is the same whether the external ramp is used or not. Figure 8 shows the simplified circuit in skip mode when both the HS-FET and the LS- FET are off. R1 R2 ESR Cout FB Vo Ro Figure 8: Simplified Circuit in Skip Mode The downward slope of the VFB ripple in skip mode can be determined with Equation (8): () REF SLOPE2 12 OUT V V (R R // Ro) C − = +× (8) Where Ro is the equivalent load resistor. As described in Figure 5, VSLOPE2 in skip mode is lower than it is in PWM mode, and the jitter is larger as well. For a system with less jitter during a light-load condition, the values of the VFB resistors should not be too large. However, this will decrease the light-load efficiency. EN Control The regulator turns on when EN is high and turns off when EN is low. For automatic start-up, pull EN up to the input voltage through a resistive voltage divider. Choose the values of the pull-up resistor (RUP from VIN to EN) and the pull-down resistor (RDOWN from EN to GND) to determine the automatic start-up voltage using Equation (9): UP DOWN IN START DOWN RR V1.25 (V) R − + =× (9) For example, if RUP = 150kΩ and RDOWN = 51kΩ, then − IN START V is 4.93V. A 10nF ceramic capacitor from EN to GND is recommended to avoid noise. There is an internal Zener diode on EN, which clamps the EN voltage to prevent runaway. EN is clamped internally using a 12V Zener diode, which limits the pull-up current to a maximum of 1mA. |
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