ADC12L080EVAL datasheet(18/23 Pages) NSC

18 / 23 page

Applications Information (Continued)

The full scale error in LSB for a sine wave input can be

described as approximately

FS =4096(1-sin (90˚ + dev))

Where dev is the angular difference between the two signals

having a 180˚ relative phase relationship to each other (see

Figure 3). Drive the analog inputs with a source impedance

less than 100

Ω.

For differential operation, each analog input signal should

have a peak-to-peak voltage equal to the input reference

voltage, V

REF, and be centered around VCM. For single-

ended operation (which will result in reduced performance),

one of the analog inputs should be connected to the d.c.

common mode voltage of the driven input. The peak-to-peak

differential input signal should be twice the reference voltage

to maximize SNR and SINAD performance (Figure 2b). For

example, set V

REF to 1.0V, bias VIN− to 1.0V and drive VIN+

with a signal range of 0V to 2.0V.

Because very large input signal swings can degrade distor-

tion performance, better performance with a single-ended

input can be obtained by reducing the reference voltage

while maintaining a full-range output. Table 1 and Table 2

indicate the input to output relationship of the ADC12L080.

The V

IN+ and the VIN− inputs of the ADC12L080 consist of

an analog switch followed by a switched-capacitor amplifier.

The internal switching action at the analog inputs causes

energy to be output from the input pins. As the driving source

tries to compensate for this, it adds noise to the signal. To

minimize this, use 33

Ω series resistors at each of the signal

inputs with a 51 pF capacitor to ground, as can be seen in

Figure 5 and Figure 6. These components should be placed

close to the ADC because the input pins of the ADC is the

most sensitive part of the system and this is the last oppor-

tunity to filter the input. The 51 pF capacitor value is for

Nyquist applications and should be replaced with a smaller

capacitor for undersampling applications. The resulting pole

should be at 1.7 to 2.0 times the highest input frequency.

When determining this capacitor value, take into consider-

ation the 8 pF ADC input capacitance.

Table 3 gives component values for Figure 5 to convert a

signals to a range 1.0V ±0.5V at each of the differential input

pins of the ADC12L080.

TABLE 3. Resistor values for Circuit of Figure 5

SIGNAL

RANGE

R5, R6

0 - 0.25V

Ω

open

200

Ω 1780Ω 1000Ω

0 - 0.5V

Ω

open

249

Ω 1400Ω 499Ω

±0.5V

100

Ω 1210Ω 100Ω 1210Ω 499Ω

3.0 DIGITAL INPUTS

Digital inputs consist of CLK, OF and PD. All digital inputs

are 3V CMOS compatible.

3.1 CLK

The CLK signal controls the timing of the sampling process.

Drive the clock input with a stable, low jitter clock signal in

the range indicated in the Electrical Table with rise and fall

times of less than 2 ns. The trace carrying the clock signal

should be as short as possible and should not cross any

other signal line, analog or digital, not even at 90˚.

The CLK signal also drives an internal state machine. If the

CLK is interrupted, or its frequency is too low, the charge on

internal capacitors can dissipate to the point where the ac-

curacy of the output data will degrade. This is what limits the

minimum sample rate.

The duty cycle of the clock signal can affect the performance

of any A/D Converter. Because achieving a precise duty

cycle is difficult, the ADC12L080 is designed to maintain

performance over a range of duty cycles. While it is specified

and performance is guaranteed with a 50% clock duty cycle,

performance is typically maintained over a clock duty cycle

range indicated in the Electrical Table.

The clock line should be terminated at its source in the

characteristic impedance of that line. Take care to maintain a

constant clock line impedance throughout the length of the

line. Refer to Application Note AN-905 for information on

setting characteristic impedance.

It is highly desirable that the the source driving the ADC CLK

pin only drive that pin. However, if that source is used to

drive other things, each driven pin should be a.c. terminated

with a series RC to ground, as shown in Figure 4, such that

the resistor value is equal to the characteristic impedance of

the clock line and the capacitor value is

where t

PD is the signal propagation rate down the clock line,

"L" is the line length and Z

O is the characteristic impedance

of the clock line. This termination should be as close as

possible to the ADC clock pin but beyond it as seen from the

clock source. Typical t

PD is about 150 ps/inch (60 ps/cm) on

FR-4 board material. The units of "L" and t

PD should be the

same (inches or centimeters).

3.2 OF

The OF pin is used to determine the digital data output

format. When this pin is high, the output formant is two’s

complement. When this pin is low the output format is offset

binary. Changing this pin while the device is operating will

result in uncertainty of the data for a few conversion cycles.

20061012

FIGURE 3. Angular Errors Between the Two Input

Signals Will Reduce the Output Level or Cause

Distortion

ADC12L080EVAL Datasheet(PDF) 18 Page - National Semiconductor (TI)

ADC12L080EVAL Datasheet(HTML) 18 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL