AD1838AS datasheet(13/24 Pages) AD

13 / 24 page

REV. 0

AD1838

–13–

The DAC serial data input mode defaults to I

2S. By changing

Bits 5, 6, and 7 in DAC Control Register 1, the mode can be

changed to RJ, DSP, LJ, or Packed Mode 256. The word width

defaults to 24 bits but can be changed by reprogramming

Bits 3 and 4 in DAC Control Register 1.

Packed Modes

The AD1838 has a packed mode that allows a DSP or other

controller to write to all DACs and read all ADCs using one

input data pin and one output data pin. Packed Mode 256

refers to the number of BCLKs in each frame. The LRCLK is

low while data from a left channel DAC or ADC is on the data

pin, and high while data from a right channel DAC or ADC

is on the data pin. DAC data is applied on the DSDATA1

pin, and ADC data is available on the ASDATA pin.

Figures 7–10 show the timing for the packed mode. Packed Mode

is only available for 48 kHz (based on MCLK = 12.288MHz) and

when the

M/S is low.

Auxiliary (TDM) Mode

A special auxiliary mode is provided to allow three external

stereo ADCs and one external stereo DAC to be interfaced to

the AD1838 to provide 8-in/8-out operation. In addition, this

mode supports glueless interface to a single SHARC DSP serial

port, allowing a SHARC DSP to access all eight channels of

analog I/O. In this special mode, many pins are redefined; see

Table II for a list of redefined pins. The auxiliary and the TDM

interfaces are independently configurable to operate as masters

or slaves. When the auxiliary interface is set as a master, by

programming the aux mode bit in ADC Control Register II, the

AUXLRCLK and AUXBCLK are generated by the AD1838.

When the auxiliary interface is set as a slave, the AUXLRCLK and

AUXBCLK need to be generated by an external ADC as shown in

Figure 13. The TDM interface can be set to operate as a master or

slave by connecting the

M/S pin to DGND or ODVDD, respec-

tively. In master mode, the FSTDM and BCLK signals are outputs

and generated by the AD1838. In slave mode, the FSTDM and

BCLK are inputs and should be generated by the SHARC. Slave

mode operation is available for 48 kHz and 96 kHz operation

(based on a 12.288 MHz or 24.576 MHz MCLK), and master

mode operation is available for 48 kHz only.

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL

12S MODE – 16 BITS TO 24 BITS PER CHANNEL

RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL

DSP MODE – 16 BITS TO 24 BITS PER CHANNEL

1/fS

NOTES

1. DSP MODE DOES NOT IDENTIFY CHANNEL.

2. LRCLK NORMALLY OPERATES AT

fS EXCEPT FOR DSP MODE WHICH IS 2

fS.

3. BCLK FREQUENCY IS NORMALLY 64

LRCLK BUT MAY BE OPERATED IN BURST MODE.

Figure 4. Stereo Serial Modes

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