AD1838AS datasheet(16/24 Pages) AD

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AD1838

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Table II. Pin Function Changes in Auxiliary Mode

Pin Name

2S Mode

Aux Mode

ASDATA (O)

2S Data Out, Internal ADC

TDM Data Out to SHARC

DSDATA1 (I)

2S Data In, Internal DAC1

TDM Data In from SHARC

DSDATA2 (I)/AAUXDATA1 (I)

2S Data In, Internal DAC2

AUX-I

2S Data In 1 (from Ext. ADC)

DSDATA3 (I)/AAUXDATA2 (I)

2S Data In, Internal DAC3

AUX-I

2S Data In 2 (from Ext. ADC)

AAUXDATA3 (I)

Not Connected

AUX-I

2S Data In 3 (from Ext. ADC)

ALRCLK (O)

LRCLK for ADC

TDM Frame Sync Out to SHARC (FSTDM)

ABCLK (O)

BCLK for ADC

TDM BCLK Out to SHARC

DLRCLK (I)/AUXLRCLK(I/O)

LRCLK In/Out Internal DACs

AUX LRCLK In/Out. Driven by Ext. LRCLK

from ADC in slave mode. In master mode,

driven by MCLK/512.

DBCLK (I)/AUXBCLK(I/O)

BCLK In/Out Internal DACs

AUX BCLK In/Out. Driven by Ext. BCLK from

ADC in slave mode. In master mode, driven by

MCLK/8.

DAUXDATA(O)

Not Connected

AUX-I

2S Data Out (to Ext. DAC)

FSTDM

INTERNAL

ADC L1

AUX_ADC L2

AUX_ADC L3

AUX_ADC L4

INTERNAL

ADC R1

AUX_ADC R2

AUX_ADC R3

AUX_ADC R4

INTERNAL

DAC L1

INTERNAL

DAC L2

INTERNAL

DAC L3

INTERNAL

DAC R1

INTERNAL

DAC R2

INTERNAL

DAC R3

MSB TDM

1ST

LEFT

RIGHT

I2S – MSB RIGHT

I2S – MSB LEFT

BCLK

TDM

ASDATA1

TDM (OUT)

ASDATA

DSDATA1

TDM (IN)

DSDATA1

AUX

LRCLK I2S

(FROM AUX ADC #1)

AUX

BCLK I2S

(FROM AUX ADC #1)

AAUXDATA1 (IN)

(FROM AUX ADC #1)

AAUXDATA2 (IN)

(FROM AUX ADC #2)

AAUXDATA3 (IN)

(FROM AUX ADC #3)

AUX BCLK FREQUENCY IS 64

FRAME RATE; TDM BCLK FREQUENCY IS 256

FRAME RATE.

MSB TDM

8TH

MSB TDM

1ST

MSB TDM

8TH

I2S – MSB RIGHT

I2S – MSB LEFT

I2S – MSB RIGHT

I2S – MSB LEFT

AUX DAC L4

AUX DAC R4

Figure 11. Aux-Mode Timing

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