LTC7124 datasheet(3/22 Pages) LINER

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LTC7124

7124fa

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ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Transient Absolute Maximum Voltages should not be applied for

more than 4% of the switching duty cycle.

Note 3: The LTC7124 is tested under pulsed load conditions such that

TJ ≈ TA. The LTC7124E is guaranteed to meet specified performance from

0°C to 85°C. Specifications over the –40°C to 125°C operating junction

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC7124I is guaranteed over the

full –40°C to 125°C operating junction temperature range. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board layout,

the rated package thermal impedance and other environmental factors.

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, unless otherwise noted. (Note 3)

TJ is calculated from the ambient TA and power dissipation PD according

to the following formula: TJ = TA + (PD • θJA)

Note 4: The Quiescent Current in active mode does not include switching

loss of the power FETs.

Note 5: The LTC7124 is tested in a proprietary test mode that connects

VFB to the output of error amplifier.

Note 6: The maximum VOUT is limited by the automatic boost refresh that

occurs in high duty cycle and dropout cases. The maximum VOUT value

listed here is guaranteed by design.

Note 7: The minimum on-time is determined by the speed of the top

switch driver and peak current comparator. The typical value listed here is

guaranteed by design.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ΔVLOAD&LINE

REG

Output Voltage Load and Line Regulation

VIN = 3.1 to 17V (Note 5)

ITH = 0.3V to 0.9V

0.3

0.5

IFB

Feedback Pin Input Current

gm(EA)

Error Amplifier Transconductance

ITH = 0.6V

300

500

700

µS

tON-MIN

Minimum On Time

(Note 7)

ISW

Top NMOS Switch Leakage

Bottom NMOS Switch Leakage

0.1

±1

µA

RDS(ON)

Top NMOS On Resistance

Bottom NMOS On Resistance

mΩ

VRUN

RUN Input High

RUN Input Low

1.0

0.3

RUN Input Current

VRUN = 12V

±100

VMODE/SYNC

Pulse Skip Mode

Burst Mode Operation

Forced Continuous Mode

INTVCC–0.4

1.0

0.3

INTVCC–1.2

VILIM

ILIM Input Threshold

Input Low

Input High

INTVCC–0.3

0.2

ILIM

Peak Current Limit

ILIM = 0V (Both Channels)

ILIM = INTVCC (Both Channels)

ILIM = Floating, Channel 1

ILIM = Floating, Channel 2

4.4

2.2

4.4

2.2

5.0

2.6

5.0

2.6

5.6

3.0

5.6

3.0

tSS

Internal Soft Start Time

1100

µs

VINTVCC

VINTVCC LDO Output Voltage

VIN1 > 4V

3.6

VINTVCC Undervoltage Lockout

VIN1 Ramping Up

2.75

2.9

3.05

VINTVCC Undervoltage Lockout Hysteresis

300

VIN Overvoltage Lockout Rising

17.9

18.4

18.9

VIN Overvoltage Lockout Hysteresis

500

fOSC

RT Programmable Oscillator Frequency

RRT = 100k

0.92

1.08

MHz

fSYNC

SYNC Capture Range

% of Programmed Frequency

125

Power Good Range

±5

±7.5

±10

RPGOOD

Power Good Resistance

650

1000

tPGOOD

PGOOD Delay

PGOOD Low to High, RRT = 100k

PGOOD High to Low, RRT = 100k

µs

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