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LTM4643 Datasheet(PDF) 11 Page - Linear Technology

Part # LTM4643
Description  Ultrathin Quad 關Module Regulator with Configurable 3A Output Array
PDF  32 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTM4643 Datasheet(HTML) 11 Page - Linear Technology

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For more information www.linear.com/LTM4643
APPLICATIONS INFORMATION
Discontinuous Conduction Mode (DCM)
In applications where low output ripple and high efficiency
at intermediate current are desired, discontinuous con-
duction mode (DCM) should be used by connecting the
MODE pin to SGND. At light loads the internal current
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for several cycles, thus
skipping cycles. The inductor current does not reverse
in this mode.
Force Continuous Conduction Mode (CCM)
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous conduction
modeoperationshouldbeused.Forcedcontinuousopera-
tion can be enabled by tying the MODE pin to INTVCC. In
this mode, inductor current is allowed to reverse during
low output loads, the COMP voltage is in control of the
current comparator threshold throughout, and the top
MOSFETalwaysturnsonwitheachoscillatorpulse.During
start-up, forced continuous mode is disabled and inductor
current is prevented from reversing until the LTM4643’s
output voltage is in regulation.
Operating Frequency
The operating frequency of the LTM4643 is optimized to
achievethecompactpackagesizeandtheminimumoutput
ripplevoltagewhilestillkeepinghighefficiency.Thedefault
operating frequency is internally set to 1.2MHz. In most
applications,noadditionalfrequencyadjustingisrequired.
If any operating frequency other than 1.2MHz is required
by application, the µModule regulator can be externally
synchronized to a clock from 850kHz to 1.5MHz.
Please note, a minimum switching frequency is required
for given VIN, VOUT operating conditions to keep a maxi-
mum peak-to-peak inductor ripple current below 2A for
the LTM4643. The peak-to-peak inductor ripple current
can be calculated as:
ΔIPK−PK =
VOUT
FS(MHz)
•
VIN – VOUT
VOUT
The maximum 2A peak-to-peak inductor ripple current
is enforced due to the nature of the valley current mode
control to maintain output voltage regulation at no load.
Frequency Synchronization and Clock In
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows all internal top MOSFET turn-on to
be locked to the rising edge of the same external clock.
The external clock frequency range must be within ±30%
around the 1.2MHz set frequency. A pulse detection circuit
is used to detect a clock on the CLKIN pin to turn on the
phase-locked loop. The pulse width of the clock has to
be at least 100ns. The clock high level must be above 2V
and clock low level below 0.3V. During the start-up of
the regulator, the phase-locked loop function is disabled.
Multichannel Parallel Operation
For loads that demand more than 3A of output current,
the LTM4643 multiple regulator channels can be easily
paralleled to provide more output current without increas-
ing input and output voltage ripples. The LTM4643 has
preset built-in phase shift between each two of the four
regulator channels which is suitable to employ a 2+2, 3+1
or 4 channels parallel operation. Table 2 gives the phase
difference between regulator channels.
Table 2. Phase Difference Between Regulator Channels
CHANNEL
CH1
CH2
CH3
CH4
Phase Difference
180°
90°
180°
Figure 1 shows a 2+2 and a 4-channels parallel concept
schematic for clock phasing.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used when all of the outputs are tied together
to achieve a single high output current design.



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