LTM4643 datasheet(14/32 Pages) LINER

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LTM4643

4643fb

For more information www.linear.com/LTM4643

APPLICATIONS INFORMATION

The RFB(SL) is the feedback resistor and the RTR(TOP)/

RTR(BOT) is the resistor divider on the TRACK/SS pin of

the slave regulator, as shown in Figure 4.

Following the upper equation, the master’s output slew

rate (MR) and the slave’s output slew rate (SR) in volts/

time is determined by:

RFB(SL)

RFB(SL) + 60.4k

RTR(BOT)

RTR(TOP) +RTR(BOT)

For example, VOUT(MA)=3.3V,MR=3.3V/msandVOUT(SL)

= 1.2V, SR = 1.2V/ms as VOUT1 and VOUT4 shown in

Figure 4. From the equation, we could solve out that

RTR4(TOP) = 60.4k and RTR4(BOT) = 13.3k is a good com-

bination. Follow the same equation, we can get the same

RTR(TOP)/RTR(BOT) resistor divider value for VOUT2 and

VOUT3.

The TRACK pins will have the 2.5µA current source on

when a resistive divider is used to implement tracking on

that specific channel. This will impose an offset on the

TRACK pin input. Smaller value resistors with the same

ratios as the resistor values calculated from the above

equation can be used. For example, where the 60.4k is

used then a 6.04k can be used to reduce the TRACK pin

offset to a negligible value.

The coincident output tracking can be recognized as a

special ratiometric output tracking which the master’s

output slew rate (MR) is the same as the slave’s output

slew rate (SR), as waveform shown in Figure 5.

From the equation we could easily find out that, in the

coincident tracking, the slave regulator’s TRACK/SS pin

resistor divider is always the same as its output voltage

divider.

RFB(SL)

RFB(SL) + 60.4k

RTR(BOT)

RTR(TOP) +RTR(BOT)

For example, RTR4(TOP) = 60.4k and RTR4(BOT) = 60.4k is

a good combination for coincident tracking for VOUT(MA)

= 3.3V and VOUT(SL) = 1.2V application.

Power Good

The PGOOD pins are open drain pins that can be used

to monitor each valid output voltage regulation. This pin

monitors a ±10% window around the regulation point. A

resistor can be pulled up to a particular supply voltage for

monitoring. To prevent unwanted PGOOD glitches dur-

ing transients or dynamic VOUT changes, the LTM4643’s

PGOOD falling edge includes a blanking delay of approxi-

mately 52 switching cycles.

Stability Compensation

The LTM4643 module internal compensation loop of each

regulator channel is designed and optimized for low ESR

ceramic output capacitors only application. Table 6 is

provided for most application requirements. An optional

100pF phase boost capacitor could help to boost up the

phase margin in all ceramic output capacitors application.

The LTpowerCAD Design Tool is available to download for

control loop optimization.

RUN Enable

Pulling the RUN pin of each regulator channel to ground

forcestheregulatorintoitsshutdownstate,turningoffboth

power MOSFETs and most of its internal control circuitry.

Bringing the RUN pin above 0.7V turns on the internal

reference only, while still keeping the power MOSFETs

off. Further increasing the RUN pin voltage above 1.2V

will turn on the entire regulator channel.

Figure 5. Output Coincident Tracking Waveform

4643 F05

TIME

VOUT4 = 1.2V

VOUT3 = 1.8V

VOUT2 = 2.5V

VOUT1 = 3.3V

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