LTC3883 datasheet(92/136 Pages) LINER

92 / 136 page

LTM4676A

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For more information www.linear.com/LTM4676A

appenDix c: pMbus coMManD DeTails

MFR_PWM_CONFIG

The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the

SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the part

must be commanded off. If the part is in the RUN state and this command is written, the command will be ignored and

a BUSY fault will be asserted. Bit 7 allows remote differential voltage sensing for PolyPhase rail applications.

BIT

MEANING

EA Connection

0 – Independent EA and Channel Outputs

1 – EA1 uses EA0 input for PolyPhase operation

Reserved.

Reserved

Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until

SVIN > VIN_ON. The SHARE_CLK pin will be

pulled low when SVIN < VIN_OFF. If this bit is 0, the SHARE_CLK

pin will not be pulled low when SVIN < VIN_OFF except for the

initial application of SVIN.

Reserved

BIT [2:0]

CHANNEL 0 (DEGREES)

CHANNEL 1 (DEGREES)

000b

180

001b

270

010b

240

011b

120

100b

120

240

101b

240

110b

120

300

Do not assert Bit [7] unless it is a PolyPhase application and both VOUT pins are tied together and both COMPna pins

are tied together.

This command has one data byte.

LTC3883 Datasheet(PDF) 92 Page - Linear Technology

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