LTC3402 datasheet(10/32 Pages) LINER

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LTC1871X

1871xf

For more information www.linear.com/LTC1871X

Figure 3. LTC1871X Burst Mode Operation

(MODE/SYNC = 0V) at Low Output Current

Figure 4. LTC1871X Low Output Current Operation with

Burst Mode Operation Disabled (MODE/SYNC = INTVCC)

VOUT

50mV/DIV

5A/DIV

10µs/DIV

1871x F03

VIN = 3.3V

VOUT = 5V

IOUT = 500mA

MODE/SYNC = 0V

(Burst Mode OPERATION)

VOUT

50mV/DIV

5A/DIV

2µs/DIV

1871x F04

VIN = 3.3V

VOUT = 5V

IOUT = 500mA

MODE/SYNC = INTVCC

(PULSE-SKIP MODE)

Figure 5. MODE/SYNC Clock Input and Switching

Waveforms for Synchronized Operation

1871x F05

2V TO 7V

MODE/

SYNC

GATE

tMIN = 25ns

0.8T

D = 40%

T = 1/fO

MOSFET RDS(ON). If the ITH pin drops below 0.30V, the

BurstModecomparatorB1willturnoffthepowerMOSFET

and scale back the quiescent current of the IC to 250µA

(sleep mode). In this condition, the load current will be

supplied by the output capacitor until the ITH voltage rises

above the 50mV hysteresis of the burst comparator. At

light loads, short bursts of switching (where the average

inductor current is 20% of its maximum value) followed

by long periods of sleep will be observed, thereby greatly

improving converter efficiency. Oscilloscope waveforms

illustrating Burst Mode operation are shown in Figure 3.

Pulse-Skip Mode Operation

With the MODE/SYNC pin tied to a DC voltage above 2V,

Burst Mode operation is disabled. The internal, 0.525V

buffered ITH burst clamp is removed, allowing the ITH

pin to directly control the current comparator from no

load to full load. With no load, the ITH pin is driven below

0.30V, the power MOSFET is turned off and sleep mode

is invoked. Oscilloscope waveforms illustrating this mode

of operation are shown in Figure 4.

When an external clock signal drives the MODE/SYNC

pin at a rate faster than the chip’s internal oscillator, the

oscillatorwillsynchronizetoit.Inthissynchronizedmode,

Burst Mode operation is disabled. The constant frequency

associated with synchronized operation provides a more

controlled noise spectrum from the converter, at the ex-

pense of overall system efficiency of light loads.

When the oscillator’s internal logic circuitry detects a

synchronizing signal on the MODE/SYNC pin, the in-

ternal oscillator ramp is terminated early and the slope

compensation is increased by approximately 30%. As

a result, in applications requiring synchronization, it is

recommended that the nominal operating frequency of

the IC be programmed to be about 75% of the external

clock frequency. Attempting to synchronize to too high an

external frequency (above 1.3fO) can result in inadequate

slopecompensationandpossiblesubharmonicoscillation

(or jitter).

The external clock signal must exceed 2V for at least 25ns,

and should have a maximum duty cycle of 80%, as shown

in Figure 5. The MOSFET turn on will synchronize to the

rising edge of the external clock signal.

OPERATION

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