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LTC4006

sn4006 4006is

Example #1: 10k

Ω NTC with custom limits

TLOW = 0

°C, THIGH = 50°C

RTH = 10k at 25°C,

RTH(LOW) = 32.582k at 0°C

RTH(HIGH) = 3.635k at 50°C

R9 = 24.55k

→ 24.3k (nearest 1% value)

R9A = 99.6k

→ 100k (nearest 1% value)

Example #2: 100k

Ω NTC

TLOW = 5

°C, THIGH = 50°C

RTH = 100k at 25°C,

RTH(LOW) = 272.05k at 5°C

RTH(HIGH) = 33.195k at 50°C

R9 = 226.9k

→ 226k (nearest 1% value)

R9A = 1.365M

→ 1.37M (nearest 1% value)

Example #3: 22k

Ω PTC

TLOW = 0

°C, THIGH = 50°C

RTH = 22k at 25°C,

RTH(LOW) = 6.53k at 0°C

RTH(HIGH) = 61.4k at 50°C

R9 = 43.9k

→ 44.2k (nearest 1% value)

R9A = 154k

Sizing the Thermistor Hold Capacitor

During the hold interval, C7 must hold the voltage across

the thermistor relatively constant to avoid false readings.

A reasonable amount of ripple on NTC during the hold

interval is about 10mV to 15mV. Therefore, the value of C7

is given by:

C7 = tHOLD/(R9/7 • –ln(1 – 8 • 15mV/4.5V))

= 10 • RRT • 17.5pF/(R9/7 • – ln(1 – 8 • 15mV/4.5V)

Example:

R9 = 24.3k

RRT = 309k (~2 hour timer)

C7 = 0.58

µF → 0.56µF (nearest value)

APPLICATIO S I FOR ATIO

Disabling the Thermistor Function

If the thermistor is not needed, connecting a resistor

between DCIN and NTC will disable it. The resistor should

be sized to provide at least 10

µAwiththeminimumvoltage

applied to DCIN and 10V at NTC. Do not exceed 30

µA into

NTC. Generally, a 301k resistor will work for DCIN less

than 15V. A 499k resistor is recommended for DCIN

between 15V and 24V.

PCB Layout Considerations

For maximum efficiency, the switch node rise and fall times

should be minimized. To prevent magnetic and electrical

field radiation and high frequency resonant problems,

proper layout of the components connected to the IC is

essential. (See Figure 12.) Here is a PCB layout priority list

for proper layout. Layout the PCB using this specific order.

1. Input capacitors need to be placed as close as possible

to switching FET’s supply and ground connections.

Shortest copper trace connections possible. These

parts must be on the same layer of copper. Vias must

not be used to make this connection.

2. The control IC needs to be close to the switching FET’s

gate terminals. Keep the gate drive signals short for a

clean FET drive. This includes IC supply pins that con-

nect to the switching FET source pins. The IC can be

placed on the opposite side of the PCB relative to above.

3. Place inductor input as close as possible to switching

FET’s output connection. Minimize the surface area of

this trace. Make the trace width the minimum amount

needed to support current—no copper fills or pours.

Avoid running the connection using multiple layers in

parallel. Minimize capacitance from this node to any

other trace or plane.

4. Place the output current sense resistor right next to

the inductor output but oriented such that the IC’s

Figure 10. Voltage Divider Thermistor Network

Figure 11. General Thermistor Network

LTC4006

NTC

RTH

4006 F10

LTC4006

NTC

R9A

RTH

4006 F11

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