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LTC2328-16

232816fb

For more information www.linear.com/LTC2328-16

aDc TiMing characTerisTics The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above VDD or

OVDD, they will be clamped by internal diodes. This product can handle

input currents up to 100mA below ground or above VDD or OVDD without

latch-up.

Note 4: VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V,

fSMPL = 1MHz.

Note 5: Recommended operating conditions.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code flickers between 0000 0000 0000 0000 and 1111

1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS

untrimmed deviation from ideal first and last code transitions and includes

the effect of offset error.

Note 8: All specifications in dB are referred to a full-scale ±10.24V input

with REFIN = 2.048V.

Note 9: When REFBUF is overdriven, the internal reference buffer must be

turned off by setting REFIN = 0V.

Note 10: fSMPL = 1MHz, IREFBUF varies proportionally with sample rate.

Note 11: Guaranteed by design, not subject to test.

Note 12: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V

and OVDD = 5.25V.

Note 13: tSCK of 10ns maximum allows a shift clock frequency up to

100MHz for rising edge capture.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSMPL

Maximum Sampling Frequency

Msps

tCONV

Conversion Time

460

527

tACQ

Acquisition Time

tACQ = tCYC – tCONV – tBUSYLH (Note 11)

460

tCYC

Time Between Conversions

µs

tCNVH

CNV High Time

tBUSYLH

CNV↑ to BUSY Delay

CL = 20pF

tCNVL

Minimum Low Time for CNV

(Note 12)

tQUIET

SCK Quiet Time from CNV↑

(Note 11)

tSCK

SCK Period

(Notes 12, 13)

tSCKH

SCK High Time

tSCKL

SCK Low Time

tSSDISCK

SDI Setup Time From SCK↑

(Note 12)

tHSDISCK

SDI Hold Time From SCK↑

(Note 12)

tSCKCH

SCK Period in Chain Mode

tSCKCH = tSSDISCK + tDSDO (Note 12)

13.5

tDSDO

SDO Data Valid Delay from SCK↑

CL = 20pF, OVDD = 5.25V

CL = 20pF, OVDD = 2.5V

CL = 20pF, OVDD = 1.71V

7.5

9.5

tHSDO

SDO Data Remains Valid Delay from SCK↑

CL = 20pF (Note 11)

tDSDOBUSYL

SDO Data Valid Delay from BUSY↓

CL = 20pF (Note 11)

tEN

Bus Enable Time After RDL↓

(Note 12)

tDIS

Bus Relinquish Time After RDL↑

(Note 12)

tWAKE

REFBUF Wake-Up Time

CREFBUF = 47μF, CREFIN = 100nF

200

Figure 1. Voltage Levels for Timing Specifications

0.8 • OVDD

0.2 • OVDD

50%

232816 F01

0.2 • OVDD

0.8 • OVDD

0.2 • OVDD

0.8 • OVDD

tDELAY

tWIDTH

tDELAY

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