LTC1150 datasheet(8/24 Pages) LINER

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LTC2758

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pin FuncTions

REFA (Pins 1, 2): Feedback Resistor for the DAC A Refer-

ence Inverting Amplifier, and Reference Input for DAC A.

The 20k feedback resistor is connected internally from

REFA to RCOMA. For normal operation tie this pin to the

output of the DAC A reference inverting amplifier (see

Typical Application). Typically –5V; accepts up to ±15V.

Pins 1 and 2 are internally shorted together.

RCOMA (Pin 3): Virtual Ground Point for the DAC A Ref-

erence Amplifier Inverting Resistors. The 20k reference

inverting resistors are connected internally from RINA to

RCOMA and from RCOMA to REFA, respectively (see Block

Diagram). For normal operation tie RCOMA to the negative

input of the external reference inverting amplifier (see

Typical Application).

GEADJA (Pin 4): Gain Adjust Pin for DAC A. This control pin

canbeusedtonullgainerrorortocompensateforreference

errors. The gain change expressed in LSB is the same for

anyoutputrange.SeeSystemOffsetandGainAdjustments

in the Operation section. Tie to ground if not used.

RINA (Pins 5, 6): Input Resistor for the DAC A External

Reference Inverting Amplifier. The 20k input resistor is

connected internally from RINA to RCOMA. For normal op-

eration tie RINA to the external positive reference voltage

(seeTypicalApplication).Eitherorbothoftheseprecision-

matched resistor sets (each set comprising RINX, RCOMX

and REFX) may be used to invert positive references to

provide the negative voltages needed by the DACs. Typi-

cally 5V; accepts up to ±15V. Pins 5 and 6 are internally

shorted together.

GND (Pins 7, 10, 15, 17, 18, 27, 30): Ground; tie to

ground.

IOUT2AS, IOUT2AF (Pins 8, 9): DAC A Current Output

Complement Sense and Force Pins. Tie to ground via a

clean, low-impedance path. These pins may be used with

a precision ground buffer amp as a Kelvin sensing pair

(see the Applications Information section).

CS/LD (Pin 11): Synchronous Chip Select and Load Input

Pin.

SDI (Pin 12): Serial Data Input. Data is clocked in on the

rising edge of the serial clock (SCK) when CS/LD is low.

SCK (Pin 13): Serial Clock Input.

SRO (Pin 14): Serial Readback Output. Data is clocked out

on the falling edge of SCK. Readback data begins clocking

out after the last address bit A0 is clocked in. SRO is an

active output only when the chip is selected (i.e., when

CS/LD is low). Otherwise SRO presents a high-impedance

output in order to allow other parts to control the bus.

VDD(Pin16):PositiveSupplyInput;2.7V≤VDD≤5.5V.By-

pass with a 0.1μF low-ESR ceramic capacitor to ground.

CLR (Pin 19): Asynchronous Clear Input. When this pin is

low, all DAC registers (both code and span) are cleared to

zero. All DAC outputs are cleared to zero volts.

RFLAG (Pin 20): Reset Flag Output. An active low output

is asserted when there is a power-on reset or a clear event.

Returns high when an Update command is executed.

DNC (Pin 21): Do Not Connect.

M-SPAN (Pin 22): Manual Span Control Pin. M-SPAN is

used in conjunction with pins S2, S1 and S0 (Pins 25, 24

and 23) to configure all DACs for operation in a single,

fixed output range.

To configure the part for manual-span use, tie M-SPAN

directly to VDD. The DAC output range is then set via

hardware pin strapping of pins S2, S1 and S0 (rather than

through the SPI port); and Write and Update commands

have no effect on the active output span.

ToconfigurethepartforSoftSpanuse,tieM-SPANdirectly

to GND. The output ranges are then individually control-

lable through the SPI port; and pins S2, S1 and S0 have

no effect.

SeeManualSpanConfigurationintheOperationsection.M-

SPAN must be connected either directly to GND (SoftSpan

configuration) or to VDD (manual-span configuration).

S0 (Pin 23): Span Bit 0 Input. In Manual Span mode (M-

SPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped

to select a single fixed output range for all DACs. These

pins should be tied to either GND or VDD even if they are

unused.

S1 (Pin 24): Span Bit 1 Input. In Manual Span mode (M-

SPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped to

select a single fixed output range for all DACs. These pins

shouldbetiedtoeitherGNDorVDDeveniftheyareunused.

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