LTC1150 datasheet(5/24 Pages) LINER

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LTC2758

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Continuous operation above the specified maximum operating

junction temperature may impair device reliability.

Note 3: Calculation from feedback resistance and IOUT1 leakage current

specifications; not production tested. In most applications, unipolar zero-

scale error is dominated by contributions from the output amplifier.

Note 4: Input resistors measured from RINX to RCOMX; feedback resistors

measured from RCOMX to REFX.

Note 5: DAC input resistance is independent of code.

Note 6: Parallel combination of the resistances from the specified pin to

IOUT1X and from the specified pin to IOUT2X.

Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0004% settling time

of 1.8µs can be achieved by optimizing the time constant on an individual

basis. See Application Note 120, 1ppm Settling Time Measurement for a

Monolithic 18-Bit DAC.

TiMing characTerisTics The

denotes specifications that apply over the full operating temperature range,

otherwise specifications are at TA = 25°C.

Note 8: Measured at the major carry transition, 0V to 5V range. Output

amplifier: LT1468; CFB = 50pF.

Note 9: Full-scale transition; REF = 0V.

Note 10: Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA,

expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and

zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave.

Note 11: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output

amplifier = LT1468.

Note 12: Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K

(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =

bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full-scale.

Note 13: Guaranteed by design; not production tested.

Note 14: When using SRO, maximum SCK frequency fMAX is limited by

SRO propagation delay t9 as follows:

fMAX =

2 t9 + tS

(

)

⎛

⎝

⎜

⎞

⎠

⎟ , where tS is the setup time of the receiving device.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CS/LD Low to SCK Positive Edge

CS/LD High to SCK Positive Edge

SRO Propagation Delay

CLOAD = 10pF

t10

CLR Pulse Width Low

t11

LDAC Pulse Width Low

t12

CLR Low to RFLAG Low

CLOAD = 10pF (Note 13)

t13

CS/LD High to RFLAG high

CLOAD = 10pF (Note 13)

SCK Frequency

50% Duty Cycle (Note 14)

MHz

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