LTC2668 datasheet(14/40 Pages) LINER

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LTC2348-16

234816fa

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pin FuncTions

CMOS I/O Mode

SDO0 to SDO7 (Pins 25, 26, 27, 28, 33, 34, 35, and 36):

CMOS Serial Data Outputs, Channels 0 to 7. The most

recent conversion result along with channel configuration

information is clocked out onto the SDO pins on each ris-

ing edge of SCKI. Output data formatting is described in

the Digital Interface section. Leave unused SDO outputs

unconnected. Logic levels are determined by OVDD.

SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with

the serial I/O clock. SCKI rising edges latch serial data in

on SDI and clock serial data out on SDO0 to SDO7. For

standard SPI bus operation, capture output data at the

receiver on rising edges of SCKI. SCKI is allowed to idle

either high or low. Logic levels are determined by OVDD.

OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O

mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD

to GND (Pin 30) close to the pin with a 0.1μF ceramic

capacitor.

SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising

edges trigger transitions on SCKO that are skew-matched

to the serial output data streams on SDO0 to SDO7. The

resulting SCKO frequency is half that of SCKI. Rising and

falling edges of SCKO may be used to capture SDO data at

the receiver (FPGA) in double data rate (DDR) fashion. For

standard SPI bus operation, SCKO is not used and should

be left unconnected. SCKO is forced low at the falling edge

of BUSY. Logic levels are determined by OVDD.

SDI(Pin37):CMOSSerialDataInput.Drivethispinwiththe

desired24-bitSoftSpanconfigurationword(seeTable 1a),

latched on the rising edges of SCKI. If all channels will be

configured to operate only in SoftSpan 7, tie SDI to OVDD.

Logic levels are determined by OVDD.

CS (Pin 39): Chip Select Input. The serial data I/O bus is

enabled when CS is low and is disabled and Hi-Z when

CS is high. CS also gates the external shift clock, SCKI.

Logic levels are determined by OVDD.

LVDS I/O Mode

SDO0, SDO7, SDI (Pins 25, 36, and 37): CMOS Serial

Data I/O. In LVDS I/O mode, these pins are Hi-Z.

SDI+, SDI– (Pins 26 and 27): LVDS Positive and Negative

Serial Data Input. Differentially drive SDI+/SDI– with the

desired 24-bit SoftSpan configuration word (see Table

1a), latched on both the rising and falling edges of SCKI+/

SCKI–. The SDI+/SDI– input pair is internally terminated

with a 100Ω differential resistor when CS is low.

SCKI+,SCKI–(Pins28and29):LVDSPositiveandNegative

Serial Clock Input. Differentially drive SCKI+/SCKI– with

the serial I/O clock. SCKI+/SCKI– rising and falling edges

latch serial data in on SDI+/SDI– and clock serial data out

on SDO+/SDO–. Idle SCKI+/SCKI– low, including when

transitioning CS. The SCKI+/SCKI– input pair is internally

terminated with a 100Ω differential resistor when CS = 0.

OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O

mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD

to GND (Pin 30) close to the pin with a 0.1μF ceramic

capacitor.

SCKO+, SCKO– (Pins 32 and 33): LVDS Positive and

Negative Serial Clock Output. SCKO+/SCKO– outputs a

copy of the input serial I/O clock received on SCKI+/SCKI–,

skew-matchedwiththeserialoutputdatastreamonSDO+/

SDO–. Use the rising and falling edges of SCKO+/SCKO–

to capture SDO+/SDO– data at the receiver (FPGA). The

SCKO+/SCKO–outputpairmustbedifferentiallyterminated

with a 100Ω resistor at the receiver (FPGA).

SDO+, SDO– (Pins 34 and 35): LVDS Positive and Nega-

tive Serial Data Output. The most recent conversion result

along with channel configuration information is clocked

out onto SDO+/SDO– on both rising and falling edges of

SCKI+/SCKI–, beginning with channel 0. The SDO+/SDO–

output pair must be differentially terminated with a 100Ω

resistor at the receiver (FPGA).

CS (Pin 39): Chip Select Input. The serial data I/O bus is

enabled when CS is low, and is disabled and Hi-Z when

CS is high. CS also gates the external shift clock, SCKI+/

SCKI–.Theinternal100Ωdifferentialterminationresistors

on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled

when CS is high. Logic levels are determined by OVDD.

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