LTC2668 datasheet(36/40 Pages) LINER

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LTC2348-16

234816fa

For more information www.linear.com/LTC2348-16

(CMOS)

PD = 0

DON’T CARE

BUSY

(CMOS)

SCKO

(LVDS)

SDO

(LVDS)

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

234816 F21

Hi-Z

CHANNEL 0 PACKET

CHANNEL 1 PACKET

CHANNEL 2 PACKET

CHANNEL3PACKET

(PARTIAL)

Hi-Z

NEW SoftSpan CONFIGURATION WORD

(OVERWRITES INTERNAL CONFIG REGISTER)

TWO ALL-ZERO WORDS AND ONE PARTIAL WORD

(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)

tEN

tDIS

Figure 21. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS

Serial LVDS Output Data Capture

As shown in Table 3, full 200ksps per channel throughput

can be achieved with a 180MHz SCKI frequency by captur-

ing eight packets (96 SCKI cycles total) of DDR data from

SDO. The LTC2348-16 supports LVDS SCKI frequencies

up to 250MHz.

Programming the SoftSpan Configuration Register in

LVDS I/O Mode

The internal 24-bit SoftSpan configuration register con-

trols the SoftSpan range for all analog input channels of

the LTC2348-16. The default state of this register after

power-up or resetting the device is all ones, configuring

each channel to convert in SoftSpan 7, the ±2.5 • VREFBUF

range (see Table 1a). The state of this register may be

modifiedbyprovidinganew24-bitSoftSpanconfiguration

word on SDI during the data transaction window shown

in Figure 20. New SoftSpan configuration words are only

accepted within this recommended data transaction win-

dow, but SoftSpan changes take effect immediately with

no additional analog input settling time required before

starting the next conversion. Setting a channel’s SoftSpan

code to SS[2:0] = 000 immediately disables the channel,

resultinginacorrespondingreductionintCONV onthenext

conversion.Similarly,enablingapreviouslydisabledchan-

nel requires no additional analog input settling time before

starting the next conversion. The mapping between the

serial SoftSpan configuration word, the internal SoftSpan

configuration register, and each channel’s 3-bit SoftSpan

code is illustrated in Figure 19.

If fewer than 24 SCKI edges (rising plus falling) are

provided during a data transaction window, the partial

word received on SDI will be ignored and the SoftSpan

configuration register will not be updated. If exactly 24

SCKI edges are provided, the SoftSpan configuration

configuration word, S[23:0]. The one exception to this

behavior occurs when S[23:0] is all zeros. In this case,

the SoftSpan configuration register will not be updated,

allowing applications to retain the current SoftSpan con-

figuration state by idling SDI low. If more than 24 SCKI

edgesareprovidedduringadatatransactionwindow,each

complete 24-bit word received on SDI will be interpreted

as a new SoftSpan configuration word and applied to the

SoftSpan configuration register as described above. Any

partial words are ignored.

Typically, applications will update the SoftSpan configura-

tion register in the manner shown in Figures 20 and 21.

After the opening of a new data transaction window at

the falling edge of BUSY, the user supplies a 24-bit DDR

SoftSpan configuration word on SDI during the first 12

SCKI cycles. This new word overwrites the internal con-

figuration register contents following the 12th SCKI falling

edge. The user then holds SDI low for the remainder of

the data transaction window causing the register to retain

its contents regardless of the number of additional SCKI

cycles applied. SoftSpan settings may be retained across

multiple conversions by holding SDI low for the entire

data transaction window, regardless of the number of

SCKI cycles applied.

applicaTions inForMaTion

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