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LTC2345-18

234518f

For more information www.linear.com/LTC2345-18

that the LTC2345-18 achieves a typical THD of –111dB

(N = 6) in the ±4.096V range at a 200kHz sampling rate

with a fully differential 2kHz input signal.

POWER CONSIDERATIONS

The LTC2345-18 provides two power supply pins: the 5V

core power supply (VDD) and the digital input/output (I/O)

interface power supply (OVDD). The flexible OVDD supply

allows the LTC2345-18 to communicate with CMOS logic

operating between 1.8V and 5V, including 2.5V and 3.3V

systems. When using LVDS I/O mode, the range of OVDD

is 2.375V to 5.25V.

Power Supply Sequencing

The LTC2345-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2345-18 has

an internal power-on-reset (POR) circuit which resets the

converter on initial power-up and whenever VDD drops

below 2V. Once the supply voltage re-enters the nominal

supply voltage range, the POR reinitializes the ADC. No

conversions should be initiated until at least 10ms after

a POR event to ensure the initialization period has ended.

Whenemployingtheinternalreferencebuffer,allow200ms

forthebuffertopowerupandrechargetheREFBUFbypass

capacitor. Any conversion initiated before these times will

produce invalid results.

TIMING AND CONTROL

CNV Timing

TheLTC2345-18samplingandconversioniscontrolledby

CNV. A rising edge on CNV transitions all channels’ S/H

circuits from track mode to hold mode, simultaneously

sampling the input signals on all channels and initiating

a conversion. Once a conversion has been started, it

cannot be terminated early except by resetting the ADC,

as discussed in the Reset Timing section. For optimum

performance, drive CNV with a clean, low jitter signal and

avoid transitions on data I/O lines leading up to the rising

edgeofCNV.Additionally,tominimizechannel-to-channel

crosstalk, avoid high slew rates on the analog inputs for

100ns before and after the rising edge of CNV. Converter

status is indicated by the BUSY output, which transitions

low-to-high at the start of each conversion and stays high

untiltheconversioniscomplete. OnceCNVisbroughthigh

to begin a conversion, it should be returned low between

40ns and 60ns later or after the falling edge of BUSY to

minimizeexternaldisturbancesduringtheinternalconver-

sion process. If CNV is returned low after the falling edge

of BUSY, it should be held low for at least 420ns before

bringing it high again, since the converter acquisition

time (tACQ) is set by the CNV low time (tCNVL) in this case.

Internal Conversion Clock

The LTC2345-18 has an internal clock that is trimmed to

achieve a maximum conversion time of 555 • N – 35ns

withNchannelsenabled.Withaminimumacquisitiontime

of 565ns when converting eight channels simultaneously,

throughputperformanceof200kspsisguaranteedwithout

any external adjustments.

Power Down Mode

When PD is brought high, the LTC2345-18 is powered

down and subsequent conversion requests are ignored. If

this occurs during a conversion, the device powers down

once the conversion completes. In this mode, the device

draws only a small regulator standby current resulting in a

typical power dissipation of 0.33mW. To exit power down

mode, bring the PD pin low and wait at least 10ms before

initiating a conversion. When employing the internal refer-

ence buffer, allow 200ms for the buffer to power up and

recharge the REFBUF bypass capacitor. Any conversion

initiated before these times will produce invalid results.

Reset Timing

A global reset of the LTC2345-18, equivalent to a power-

on-reset event, may be executed without needing to cycle

the supplies. This feature is useful when recovering from

system-level events that require the state of the entire sys-

applicaTions inForMaTion

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