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LTC2345-18

234518f

For more information www.linear.com/LTC2345-18

tem to be reset to a known synchronized value. To initiate

a global reset, bring PD high twice without an intervening

conversion, as shown in Figure 15. The reset event is trig-

geredonthesecondrisingedgeofPD,andasynchronously

ends based on an internal timer. Reset clears all serial data

outputregistersandrestorestheinternalSoftSpanconfigu-

ration register default state of all channels in SoftSpan 7.

If reset is triggered during a conversion, the conversion

is immediately halted. The normal power down behavior

associatedwithPDgoinghighisnotaffectedbyreset.Once

PD is brought low, wait at least 10ms before initiating a

conversion. When employing the internal reference buffer,

allow 200ms for the buffer to power up and recharge the

REFBUF bypass capacitor. Any conversion initiated before

these times will produce invalid results.

Auto Nap Mode

The LTC2345-18 automatically enters nap mode after a

conversion has finished and completely powers up once a

new conversion is initiated on the rising edge of CNV. Auto

nap mode causes the power dissipation of the LTC2345-

18 to decrease as the sampling frequency is reduced,

as shown in Figure 16. This decrease in average power

dissipation occurs because a portion of the LTC2345-18

circuitry is turned off during nap mode, and the fraction

of the conversion cycle (tCYC) spent napping increases as

the sampling frequency (fSMPL) is decreased.

applicaTions inForMaTion

DIGITAL INTERFACE

TheLTC2345-18featuresCMOSandLVDSserialinterfaces,

selectable using the LVDS/CMOS pin. The flexible OVDD

supply allows the LTC2345-18 to communicate with any

CMOS logic operating between 1.8V and 5V, including

2.5V and 3.3V systems, while the LVDS interface supports

low noise digital designs. In CMOS mode, applications

may employ between one and eight lanes of serial data

output, allowing the user to optimize bus width and data

Figure 16. Power Dissipation of the LTC2345-18

Decreases with Decreasing Sampling Frequency

CNV

tCONV

tCNVH

tPDH

tPDL

BUSY

RESET

RESET TIME

SET INTERNALLY

SECOND RISING EDGE OF

PD TRIGGERS RESET

tWAKE

234518 F15

Figure 15. Reset Timing for the LTC2345-18

IOVDD

IVDD

SAMPLING FREQUENCY (kHz)

120

160

200

234518 F16

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