LTC4232 datasheet(11/20 Pages) LINER

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LTC4234

4234fa

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APPLICATIONS INFORMATION

allows the inrush current to stay under the folded back

currentlimitthreshold(5.7A)forcapacitorslessthan10mF.

IncludedintheTypicalPerformanceCharacteristicssection

is a graph of the Safe Operating Area for the MOSFET. It

is evident from this graph that the power dissipation at

12V, 350mA for 34ms is in the safe region.

Adding a capacitor and a 100k series resistor from GATE to

groundwilllowertheinrushcurrentbelowthedefaultvalue

set by the INRUSH circuit. The 3.3nF capacitor, CCOMP, is

necessary to compensate the current limit regulation loop

when the RGATE and CGATE network is on the GATE pin.

The GATE is charged with a 24µA current source (when

the INRUSH circuit is not driving the GATE). The voltage

at the GATE pin rises with a slope equal to 24µA/CGATE

and the supply inrush current is set at:

IINRUSH =

CGATE

•24µA

When the GATE voltage reaches the MOSFET threshold

voltage, the switch begins to turn on and the OUT volt-

age follows the GATE voltage as it increases. Once OUT

reaches VDD, the GATE will ramp up until clamped by the

6.1V Zener between GATE and OUT.

As the OUT voltage rises, so will the FB pin which is moni-

toring it. Once the FB pin crosses its 1.235V threshold

and the GATE to OUT voltage exceeds 4.2V, the PG pin

will cease to pull low and indicate that the power is good.

Parasitic MOSFET Oscillation

When the N-channel MOSFET ramps up the output during

power-up it operates as a source follower. The source fol-

lowerconfigurationmayself-oscillateintherangeof25kHz

to 300kHz when the load capacitance is less than 10µF,

especially if the wiring inductance from the supply to VDD

pin is greater than 3µH. The possibility of oscillations will

increase as the load current (during power-up) increases.

There are two ways to prevent this type of oscillation. The

simplest way is to avoid load capacitances below 10µF.

For wiring inductances larger than 20µH, the minimum

load capacitance may extend to 100µF. A second choice

is to connect an external gate capacitor CP > 1.5nF as

shown in Figure 3.

Figure 3. Compensation for Small CLOAD

4234 F03

LTC4234

GATE

2.2nF

OPTIONAL

RC TO LOWER

INRUSH CURRENT

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by the UV pin going below its

1.235V threshold. Additionally, several fault conditions

will turn off the switch. These include an input overvolt-

age (OV pin), overcurrent circuit breaker (SENSE– pin) or

overtemperature. Normally the switch is turned off with a

250µA current pulling down the GATE pin to ground. With

the switch turned off, the OUT voltage drops which pulls

the FB pin below its threshold. The PG then pulls low to

indicate output power is no longer good.

If VDD drops below 2.65V for greater than 5µs or INTVCC

drops below 2.5V for greater than 1µs, a fast shut down

of the switch is initiated. The GATE is pulled down with a

140mA current to the OUT pin.

Overcurrent Fault

The LTC4234 features an adjustable current limit with

foldback that protects against short circuits and exces-

sive load current. To protect against excessive power

dissipation in the switch during active current limit, the

available current is reduced as a function of the output

voltage sensed by the FB pin. A graph in the Typical Per-

formance Characteristics curves shows the Current Limit

Threshold Foldback.

Anovercurrentfaultoccurswhenthecurrentlimitcircuitry

has been engaged for longer than the timeout delay set

by the TIMER. Current limiting begins when the MOSFET

currentreaches5.7Ato22.5A(dependingonthefoldback).

The GATE pin is then brought down with a 140mA GATE-

to-OUT current. The voltage on the GATE is regulated in

order to limit the current to 22.5A. At this point, a circuit

breaker time delay starts by charging the external timing

capacitor with a 100µA pull-up current from the TIMER

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