LT1356 datasheet(33/40 Pages) LINER

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LTC2358-16

Rev A

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Iffewerthan24SCKIrisingedgesareprovidedduringadata

transactionwindow,thepartialwordreceivedonSDIwillbe

ignored and the SoftSpan configuration register will not be

updated. If exactly 24 SCKI rising edges are provided, the

SoftSpan configuration register will be updated to match

the received SoftSpan configuration word, S[23:0]. The

one exception to this behavior occurs when S[23:0] is all

zeros. In this case, the SoftSpan configuration register

will not be updated, allowing applications to retain the

current SoftSpan configuration state by idling SDI low. If

more than 24 SCKI rising edges are provided during a data

transaction window, each complete 24-bit word received

on SDI will be interpreted as a new SoftSpan configuration

word and applied to the SoftSpan configuration register

as described above. Any partial words are ignored.

Typically, applications will update the SoftSpan configura-

tion register in the manner shown in Figures 16 and 17.

After the opening of a new data transaction window at the

falling edge of BUSY, the user supplies a 24-bit SoftSpan

configuration word on SDI during the first 24 SCKI cycles.

Thisnewwordoverwritestheinternalconfigurationregister

contentsfollowingthe24thSCKIrisingedge.Theuserthen

holds SDI low for the remainder of the data transaction

windowcausingtheregistertoretainitscontentsregardless

of the number of additional SCKI cycles applied. SoftSpan

settings may be retained across multiple conversions by

holding SDI low for the entire data transaction window,

regardless of the number of SCKI cycles applied.

Serial LVDS I/O Mode

In LVDS I/O mode, information is transmitted using posi-

tive and negative signal pairs (LVDS+/LVDS−) with bits

differentially encoded as (LVDS+ − LVDS−). These signals

are typically routed using differential transmission lines

S23

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5

DON’T CARE

SCKI

SDI

SoftSpan CONFIGURATION WORD

CMOS I/O MODE

SoftSpan CONFIGURATION WORD

INTERNAL 24-BIT SoftSpan CONFIGURATION REGISTER

(SAME FOR CMOS AND LVDS)

LVDS I/O MODE

tSCKI

S23

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5

DON’T CARE

SCKI

(LVDS)

SDI

(LVDS)

tSCKI

CHANNEL 7 SoftSpan

CODE SS[2:0]

CHANNEL 6 SoftSpan

CODE SS[2:0]

CHANNEL 5 SoftSpan

CODE SS[2:0]

CHANNEL 4 SoftSpan

CODE SS[2:0]

CHANNEL 3 SoftSpan

CODE SS[2:0]

CHANNEL 2 SoftSpan

CODE SS[2:0]

CHANNEL 1 SoftSpan

CODE SS[2:0]

CHANNEL 0 SoftSpan

CODE SS[2:0]

235816 F18

tSCKIH

tSCKIL

tSSDISCKI

tHSDISCKI

tSCKIH

tSCKIL

tHSDISCKI

tSSDISCKI

Figure 18. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan

Configuration Register, and SoftSpan Code for Each Analog Input Channel

APPLICATIONS INFORMATION

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