LTC4306 datasheet(9/16 Pages) LINER

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LTC4318

4318fa

For more information www.linear.com/LTC4318

Figure 4. Two Slaves Sharing One Channel of LTC4318

Figure 3. Two Independent Address Translation

operaTion

SCL

SDA

4318 F03

MASTER

SCLOUT1

SDAOUT1

SCLIN1

SDAIN1

SCL

SDA

SLAVE

LTC4318

SCLIN2

SDAIN2

SCLOUT2

SDAOUT2

SLAVE #3

INPUT ADDRESS

0x36

TRANSLATION BYTE

0x02

SCL

SDA

SLAVE

SCL

SDA

SLAVE

HARDWIRED ADDRESS

0x34

SLAVE #1

INPUT ADDRESS

0x32

TRANSLATION BYTE

0x06

HARDWIRED ADDRESS

0x34

HARDWIRED ADDRESS

0x34

00110010

00000110

00110100

00110110

00000010

00110100

SCL

SDA

4318 F04

MASTER

SCL

SDA

SLAVE

SCLOUT

SDAOUT

SCLIN

SDAIN

SCL

SDA

SLAVE

LTC4318

SCL

SDA

SLAVE

HARDWIRED ADDRESS

0x34

TRANSLATION BYTE

0x02

SLAVE #1

INPUT ADDRESS

0x36

SLAVE #3

INPUT ADDRESS

0x32

HARDWIRED ADDRESS

0x34

HARDWIRED ADDRESS

0x30

00110110

00000010

00110100

00110010

00000010

00110000

System Configurations

There are several ways that individual slaves or banks of

slaves can be connected to an LTC4318. In Figure 3, each

slave is paired with one channel of the LTC4318. This

configuration allows for maximum flexibility in allocating

the bus addresses. Both read and write operations and all

protocols supported by the LTC4318 are allowed. Figure 4

shows two slaves with different hardwired addresses

translated to two different addresses using one channel of

the LTC4318 and a common translation byte. A program

is available to help the user visualize an I2C bus with the

LTC4318; this program can be found in the following link:

www.linear.com/TranslatorTool

Setting the Translation Byte

When the LTC4318 is first powered up or any time a rising

edge is detected on the ENABLE pin, the LTC4318 reads

the voltages at the XORH and XORL pins to determine the

7-bit translation byte. These voltages are referenced to

VCC so a resistive divider at each of these pins is the most

convenient way to set the voltages. The required transla-

tion byte can be determined by taking the bitwise XOR of

the slave’s original address and the desired input address.

The voltages at the XORH and XORL pins configure the

translation byte. The XORL voltage configures the lower 4

translation bits (excluding the R/W bit), while the XORH

voltage configures the upper 3 translation bits. Tables 2

and 3 show the recommended resistive divider values. RLT

and RLB are the top and bottom resistors connected to

XORL, while RHT and RHB are the top and bottom resistors

connected to XORH (Figure 5). Use 1% tolerance resistors

for RLT, RLB, RHT and RHB.

Figure 5. Address Translation Byte Configuration Resistors

4318 F05

VCC

RHT

RLT

XORL

XORH

LTC4318

VCC

RHB

RLB

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