HSP50210 datasheet(39/51 Pages) RENESAS

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HSP50210

FN3652 Rev.5.00

Page 39 of 51

Jul 2, 2008

13-9

Symbol Tracking

Lead Gain Exponent

(Acquisition)

These bits set the lead gain exponent as given by:

Symbol Tracking Lead Gain Exponent = 2 -(32-E),

where E corresponds to the 5-bit binary value programmed here. Thus, a gain range from

2-1 to 2-32 relative to the MSB position of the NCO control word may be achieved for E = 11111 to 00000

Binary. Bit position 13 is the MSB.

8-5

Symbol Tracking Lag

Gain Mantissa

(Acquisition)

Format same as lead gain mantissa. Bit position 8 is the MSB.

4-0

Symbol Tracking Lag

Gain Exponent

(Acquisition)

Format same as lead gain exponent. Bit position 4 is the MSB.

TABLE 32. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER (Continued)

DESTINATION ADDRESS = 17

BIT

POSITION

FUNCTION

DESCRIPTION

TABLE 33. SYMBOL TRACKING LOOP FILTER GAIN (TRK) CONTROL REGISTER

DESTINATION ADDRESS = 18

BIT

POSITION

FUNCTION

DESCRIPTION

31-24

Not Used

No programming required.

23-18

Reserved

Reserved. Set to 0 for proper operation.

17-14

Symbol Tracking Lead Gain Mantissa

(Track)

Format same as lead gain mantissa (see Table 32). Bit position 17 is the MSB.

13-9

Symbol Tracking Lead Gain Exponent

(Track)

Format same as lead gain exponent (see Table 32). Bit position 13 is the MSB.

8-5

Symbol Tracking Lag Gain Mantissa

(Track)

Format same as lead gain mantissa (see Table 32). Bit position 8 is the MSB.

4-0

Symbol Tracking Lag Gain Exponent

(Track)

Format same as lead gain exponent (see Table 32). Bit position 4 is the MSB.

TABLE 34. SYMBOL TRACKING LOOP FILTER LAG ACCUMULATOR INITIALIZATION CONTROL REGISTER

DESTINATION ADDRESS = 19

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Symbol Tracking Loop

Filter Lag Accumulator

Initialization

Writing to this address initializes the lag accumulator with the contents of the four Microprocessor

Interface Holding Registers at the start of the next loop filter computation cycle. The contents of the

holding registers should not be changed until after the start of a new compute cycle since the current

contents of the holding registers are loaded at the compute cycle start. At a slow rate, it could take 1 low

rate symbol time to change. The Microprocessor Interface should be used to read an internal status

Interface” on page 27). The contents of the holding registers are loaded into the 32 MSBs of the lag

accumulator and the 8 LSBs are zeroed.

It is a good practice to load the LAG accumulators at the very end of a configuration load sequence.

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