8

Integrated

Circuit

Systems, Inc.

ICS9FG104

0839D—06/02/05

SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

RW

Pin 17

Bit 6

RW

Pin 6

Bit 5

RW

Pin 24

Bit 4

RW

Pin 25

Bit 3

RW

Off

On

Pin 16

Bit 2

RW

Hardware

Select

Software

Select

0

Bit 1

RW

Driven

Hi-Z

0

Bit 0

RW

Down

Center

0

Notes:

1. These bits reflect the state of the corresponding pins at power up, but may be written to

if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.

SMBus Table: Output Enable Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

1

Bit 6

DIF_3 EN

Output Enable

RW

Disable

Enable

1

Bit 5

DIF_2 EN

Output Enable

RW

Disable

Enable

1

Bit 4

1

Bit 3

1

Bit 2

DIF_1 EN

Output Enable

RW

Disable

Enable

1

Bit 1

DIF_0 EN

Output Enable

RW

Disable

Enable

1

Bit 0

1

SMBus Table: Output Stop Control Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

0

Bit 6

DIF_3 STOP EN Free Run/ Stop Enable RW

Free-run Stop-able

0

Bit 5

DIF_2 STOP EN Free Run/ Stop Enable RW

Free-run Stop-able

0

Bit 4

0

Bit 3

0

Bit 2

DIF_1 STOP EN Free Run/ Stop Enable RW

Free-run Stop-able

0

Bit 1

DIF_0 STOP EN Free Run/ Stop Enable RW

Free-run Stop-able

0

Bit 0

0

Reserved

Reserved

Reserved

See Frequency

Selection Table,

Page 1

SEL14M_25M#

1

(FS3)

FS2

1

FS1

1

FS0

1

-

-

-

-

-

-

-

Byte 2

-

-

-

-

-

-

Byte 1

-

-

-

DIF_STOP# drive mode

SPREAD TYPE

16

Spread Enable

1

-

Enable Software Control of Frequency,

Spread Enable (Spread Type always

Software Control)

24

25

Byte 0

17

6

Reserved

Reserved

Reserved

Reserved

Reserved