NT5DS64M4AT datasheet(22/27 Pages) ETC

22 / 27 page

NT5DS64M4AT NT5DS64M4AW

NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Preliminary

10/01

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Electrical Characteristics & AC Timing - Absolute Specifications

°C ≤ T

A ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)

Symbol

Parameter

DDR333

(-6)

DDR300

(-66)

Unit

Notes

Min

Max

Min

Max

tAC

DQ output access time from CK/CK

− 0.7

+ 0.7

− 0.75

+ 0.75

1-4

tDQSCK

DQS output access time from CK/CK

− 0.7

+ 0.7

− 0.75

+ 0.75

1-4

tCH

CK high-level width

0.45

0.55

0.45

0.55

tCK

1-4

tCL

CK low-level width

0.45

0.55

0.45

0.55

tCK

1-4

tCK

Clock cycle time

CL = 2.5

6.6

1-4

CL = 2.0

7.5

tDH

DQ and DM input hold time

0.45

0.5

1-4,

15,16

tDS

DQ and DM input setup time

0.45

0.5

1-4,

15,16

tDIPW

DQ and DM input pulse width (each input)

1.75

1-4

tHZ

Data-out high-impedance time from CK/CK

− 0.7

+ 0.7

− 0.75

+ 0.57

1-4, 5

tLZ

Data-out low-impedance time from CK/CK

− 0.7

+ 0.7

− 0.75

+ 0.75

1-4, 5

tDQSQ

DQS-DQ skew (DQS & associated DQ signals)

+ 0.4

+ 0.5

1-4

tHP

minimum half clk period for any given cycle;

defined by clk high (tCH) or clk low (tCL) time

min

(tCH,tCL)

min

(tCH,tCL)

tCK

1-4

tQH

Data output hold time from DQS

tHP - tQHS

tCK

1-4

tDQSS

Write command to 1st DQS latching

transition

0.75

1.25

0.75

1.25

tCK

1-4

tDQSL,H

DQS input low (high) pulse width (write cycle)

0.35

tCK

1-4

tDSS

DQS falling edge to CK setup time (write cycle)

0.2

tCK

1-4

tDSH

DQS falling edge hold time from CK (write cycle)

0.2

tCK

1-4

tMRD

Mode register set command cycle time

2 x tCK

1-4

tWPRES

Write preamble setup time

1-4, 7

tWPST

Write postamble

0.40

0.60

0.40

0.60

tCK

1-4, 6

tWPRE

Write preamble

0.25

tCK

1-4

tIH

Address and control input hold time

(fast slew rate)

0.75

0.9

2-4,

9,11,12

tIS

Address and control input setup time

(fast slew rate)

0.75

0.9

2-4,

9,11,12

tIH

Address and control input hold time

(slow slew rate)

0.8

1.0

2-4, 10,

11,12,14

tIS

Address and control input setup time

(slow slew rate)

0.8

1.0

2-4, 10,

11,12,14

tIPW

Input pulse width

2.2

2-4, 12

tRPRE

Read preamble

0.9

1.1

0.9

1.1

tCK

1-4

tRPST

Read postamble

0.40

0.60

0.40

0.60

tCK

1-4

tRAS

Active to Precharge command

120,000

1-4

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