NT5DS64M4AT NT5DS64M4AW

NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Preliminary

10/01

12

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Truth Table 2: Clock Enable (CKE)

1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. Command n is the command registered at clock edge n, and action n is a result of command n.

4. All states and sequences not shown are illegal or reserved.

Current State

CKE n-1

CKEn

Command n

Action n

Notes

Previous

Cycle

Current

Cycle

Self Refresh

L

L

X

Maintain Self-Refresh

Self Refresh

L

H

Deselect or NOP

Exit Self-Refresh

1

Power Down

L

L

X

Maintain Power-Down

Power Down

L

H

Deselect or NOP

Exit Power-Down

All Banks Idle

H

L

Deselect or NOP

Precharge Power-Down Entry

All Banks Idle

H

L

Auto Refresh

Self Refresh Entry

Bank(s) Active

H

L

Deselect or NOP

Active Power-Down Entry

H

H

See “Truth Table 3: Current State

Bank n - Command to Bank n (Same

Bank)” on page 13

200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.