HIP6503 datasheet(7/14 Pages) RENESAS

7 / 14 page

HIP6503

FN4882 Rev 5.00

Page 7 of 14

July 21, 2005

1V8SB (Pin 3)

This pin is the output of the internal 1.8V regulator (VOUT1).

This internal regulator operates for as long as 5VSB is

applied to the HIP6503. This pin is monitored for under-

voltage events.

1V8IN (Pin 2)

This pin is the input supply for the 1.8V internal regulator’s

pass element. Connect this pin to the 3.3VDUAL/3.3VSB

output.

VCLK (Pin 6)

This pin is the output of the internal 2.5V clock chip regulator

(VOUT4). This internal regulator operates only in active

states (S0, S1/S2) and is shut off during any sleep state,

regardless of the configuration of the chip. This pin is

monitored for under-voltage events.

Description

Operation

The HIP6503 controls 5 output voltages (Refer to Figures 1,

2, and 3). It is designed for microprocessor computer

applications with 3.3V, 5V, 5VSB, and 12V bias input from an

ATX power supply. The IC is composed of three linear

controllers/regulators supplying the computer system’s

1.8VSB (VOUT1), 3.3VSB and PCI slots’ 3.3VAUX power

(VOUT3), the 2.5V RDRAM and 3.3V SDRAM memory

power (VOUT2), an integrated regulator dedicated to 2.5V

clock chip (VOUT4), a dual switch controller supplying the

5VDUAL voltage (VOUT5), as well as all the control and

monitoring functions necessary for complete ACPI

implementation.

Initialization

The HIP6503 automatically initializes upon receipt of input

power. The Power-On Reset (POR) function continually

monitors the 5VSB input supply voltage, initiating

3.3VDUAL/3.3VSB and 1.8VSB soft-start operation shortly

after exceeding POR threshold. At 3ms (typically) after these

two outputs finish their ramp-up, the EN5VDL and MSEL

status is latched in and the chip proceeds to ramp up the

remainder of the voltages, as required.

Operational Truth Table

The EN5VDL pin offers the choice of supporting or disabling

5VDUAL output in S3 and S4/S5 sleep states. Table 1

describes the truth combinations pertaining to this output.

The internal circuitry does not allow the transition from an S3

(suspend to RAM) state to an S4/S5 (suspend to disk/soft

off) state or vice versa. The only ‘legal’ transitions are from

an active state (S0, S1) to a sleep state (S3, S5) and vice

versa.

Functional Timing Diagrams

Figures 4 through 6 are timing diagrams, detailing the power

up/down sequences of all three outputs in response to the

status of the enable (EN5VDL) and sleep-state pins (S3,

S5), as well as the status of the ATX supply.

The status of the EN5VDL pin can only be changed while in

active (S0, S1) states, when the bias supply (5VSB pin) is

below POR level, or during chip shutdown (SS pin shorted to

GND or within 3ms of 5VSB POR); a status change of this

pin while in a sleep state is ignored.

TABLE 1. 5VDUAL OUTPUT (VOUT5) TRUTH TABLE

EN5VDL

5VDL

COMMENTS

S0, S1 States (Active)

Note

Maintains Previous State

S4/S5

S0, S1 States (Active)

Note

Maintains Previous State

S4/S5

NOTE: Combination Not Allowed.

FIGURE 4. 5VDUAL TIMING DIAGRAM FOR EN5VDL = 1;

3.3VDUAL/3.3VSB

5VSB

3.3V,

5VDLSB

DLA

3V3DLSB

3V3DL

5VDL

5V, 12V

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