HIP6503

FN4882 Rev 5.00

Page 9 of 14

July 21, 2005

rather awaits until the main ATX outputs are well within

regulation limits.

SOFT-START INTO ACTIVE STATES (S0, S1)

If both S3 and S5 are logic high at the time the 5VSB is

applied, the HIP6503 will assume active state wake-up and

keep off the required outputs until some time (typically 25ms)

after the ATX’s main outputs used by the application (3.3V,

5V, and 12V) exceed the set thresholds. This time-out

feature is necessary in order to insure the main ATX outputs

are stabilized. The time-out also assures smooth transitions

from sleep into active when sleep states are being

right after bias voltage surpasses POR level.

During sleep to active state transitions from conditions

where the outputs are initially 0V (such as S5 to S0 transition

sequence directly into active state), the memory (in 3.3V

being pulled high through the body diodes of the N-Channel

MOSFETs connected between these outputs and the 3.3V

and 5V ATX outputs. Figure 8 shows this start-up case,

5VSB is already present when the main ATX outputs are

of Q5 (see Figure 3). At time T1, all main ATX outputs

exceed the HIP6503’s undervoltage thresholds, and the

internal 25ms (typical) timer is initiated. At T2 the time-out

initiates a soft-start, and the 2.5V memory and clock outputs

are ramped-up, reaching regulation limits at time T3.

Simultaneous with the beginning of the memory and clock

voltage ramp-up, at time T2, the DLA pin is pulled high,

turning on Q3 and Q5 in the process, and bringing the

voltage reaches 2.75V, the soft-start capacitor is quickly

discharged down to approximately 2.45V, where it remains

until a valid sleep state request is received from the system.

Fault Protection

All the outputs are monitored against undervoltage events. A

severe overcurrent caused by a failed load on any of the

outputs, would, in turn, cause that specific output to

suddenly drop. If any of the output voltages drops below

80% (typical) of their set value, such event is reported by

having the FAULT/MSEL pin pulled to 5V. Additionally,

exceeding the maximum current rating of an integrated

regulator (output with pass regulator on chip) can lead to

output voltage drooping; if excessive, this droop can

ultimately trip the under-voltage detector and send a FAULT

signal to the computer system.

A FAULT condition occurring on an output when controlled

through an external pass transistor will only set off the

FAULT flag, and it will not shut off or latch off any part of the

circuit. A FAULT condition occurring on an output when

controlled through an internal pass transistor, will set off the

FAULT flag, and it will shut off the respective faulting

regulator only. If shutdown or latch off of the entire circuit is

desired in case of a fault, regardless of the cause, this can

be achieved by externally pulling or latching the SS pin low.

Pulling the SS pin low will also force the FAULT pin to go low

and reset any internally latched-off output.

Special consideration is given to the initial start-up

sequence. If, following a 5VSB POR event, any of the

subject to an undervoltage event before the remainder of the

controlled voltages have been brought up, then the FAULT

output goes high and the entire IC latches off. Latch-off

according to the description found in the second paragraph

under the current heading.

Another condition that could set off the FAULT flag is chip

over-temperature. If the HIP6503 reaches an internal

temperature of 140°C (typical), the FAULT flag is set off, but

the chip continues to operate until the temperature reaches

155°C (typical), when unconditional shutdown of all outputs

takes place. Operation resumes at 140°C and the

temperature cycling occurs until the fault-causing condition

is removed.

FIGURE 8. SOFT-START INTERVAL IN ACTIVE STATE

0V

0V

TIME

OUTPUT

(1V/DIV)

VOLTAGES

T1

T2

T3

T0

INPUT VOLTAGES

(2V/DIV)

+5VSB

DLA PIN

(2V/DIV)

SOFT-START

(1V/DIV)