MP2624GL datasheet(25/45 Pages) MPS

25 / 45 page

MP2624 – 4.5A SW CHARGER W/ I2C CONTROL, NVDC POWER PATH, USB OTG

MP2624 Rev.1.05

www.MonolithicPower.com

4/9/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

USB Timer

The total charging timer in default mode from the

100mA USB source is limited by a 45 minute

timer. When this timer expires, the MP2624 stops

the converter and goes into high-Z mode.

Once the device enters the HIZ state in host

mode, it stays in HIZ until the host writes REG00

[7] to 0. When the processor starts-up, it is

recommended to first check if the charger is in

HIZ mode or not.

In default mode, the charger will reset REG00 [7]

back to 0 when the input source is removed.

When another power source is plugged in, the

charger will run detection again and update the

current limit.

Host Mode and Default Mode

The MP2624 is a host-controlled device. After the

power-on reset, the MP2624 starts in the

watchdog timer expiration state or default mode.

All the registers are in the default settings.

Any write to the MP2624 makes it transition into

host mode. All the device parameters are

programmable by the host. To keep the device in

host mode, the host has to reset the watchdog

timer regularly by writing 1 to REG01 Bit [6]

before the watchdog timer expires. Once the

watchdog timer expires, the MP2624 returns to

default mode.

VREF LDO Output

The VREF LDO supplies the internal bias circuits

as well as the high-side and low-side FET gate

drive. The pull-up rail of STAT can be connected

to VREF as well. The VREF LDO will be enabled

once OTG is enabled. In non-OTG mode, the

internal VREF LDO is enabled when the following

conditions are valid:



VIN > 3.3V



No thermal shutdown

Both the internal LDO output and VBATT will be

passed to VREF via a PMOS. Only when

VIN > VBATT +250mV, the internal LDO output will

be delivered to VREF.

The VREF power supply circuit is shown in

Figure 11.

Figure 12 shows the host mode and default

mode change flow chart.

BATT

LDO

VREF

Control

Figure 11: VREF Power Supply Circuit

Thermal Regulation and Thermal Shutdown

The MP2624 monitors continuously the internal

junction temperature to maximize power delivery

and avoid overheating the chip. When the

internal junction temperature reaches the preset

threshold, the MP2624 starts to reduce the

charge

current

prevent

higher

power

dissipation.

When the junction temperature reaches 150°C,

the PWM step-down converter goes

into

shutdown mode.

Battery Discharge Function

If only the battery is connected and the input

source is absent (but the OTG function is

disabled), the battery FET is turned on

completely when VBATT is above the VBATT_UVLO

threshold. The 10mΩ battery FET minimizes the

conduction loss during discharge and VREF LDO

stays off. The quiescent current of the MP2624 is

as low as 20μA. The low on resistance and low

quiescent current help extend the running time of

the battery.

There is an over-current limit designed in the

MP2624 to avoid system over current when the

battery is discharging. Once the discharged

current exceeds this limit (IDSG_LMT in EC Table) for

a 20μs blanking time, the discharge FET is

turned off. After a one second recovery time, the

discharge FET is turned on again.

MP2624GL Datasheet(PDF) 25 Page - Monolithic Power Systems

MP2624GL Datasheet(HTML) 25 Page - Monolithic Power Systems

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