SDIO Connector

(3.3V IO)

SD Controller

(1.8V IO)

LSF0102-Q1

SDIO level translator

Device PCB

TP1

TP2

GND

Vref_A

EN

Vref_B

A1

A2

B1

B2

LSF0102-Q1

Short Signal Trace as possible

Minimize Stub as possible

1

2

3

4

5

6

7

8

13

LSF0102-Q1

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SDLS969 – MAY 2018

Product Folder Links: LSF0102-Q1

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(1)

Vref_A is required to be the lowest voltage level across all inputs and outputs.

10 Power Supply Recommendations

There are no power sequence requirements for the LSF family. For recommended operating voltages for all

supply and input pins, see Table 5.

Table 4. Recommended Operating Voltages

PARAMETER

MIN

TYP

MAX

UNIT

reference voltage (A)

0.95

4.5

V

Vref_B

reference voltage (B)

Vref_A + 0.8

5.5

V

input voltage on EN pin

Vref_A + 0.8

5.5

V

Vpu

pull-up supply voltage

0

Vref_B

V

11 Layout

11.1 Layout Guidelines

Because the LSF0102-Q1 device is a switch-type level translator, the signal integrity is dependent upon the pull-

up resistor value and PCB board parasitics. Consider the following recommendations when designing with the

LSF0102-Q1.

•

Minimize the signal trace length to reduce capacitance

•

Avoid using stubs in the signal path to reduce parasitics.

•

Place the LSF0102-Q1 device near the high voltage side.

•

Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

11.2 Layout Example

Figure 9. Short Trace Layout

Figure 10. Device Placement