ISL6534CVZ datasheet(13/29 Pages) RENESAS

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ISL6534

FN9134 Rev 2.00

Page 13 of 29

Nov 18, 2005

The soft-start pins can share the same capacitor, to ramp

them all at the same rate (but since there will be 3 times the

current, the value of the capacitor needs to be approximately

3 times bigger, for the same ramp rate).

Note that each output rise does not start until its SS/EN

voltage reaches ~1V; the output will then start to ramp up

until the soft-start is > ~3.3V (ramp is done). PGOOD will not

go active unless all three ramps are >3.3V (and no faults are

detected).

Figure 9 shows the start-up waveform for VOUT1 at power

up. In this example, the VCC voltage is generated from the

internal shunt regulator. The ramp of the 12V is controlled by

the external power supply; it can vary widely, depending

upon the type and model used. The ramp of the shunt more

or less follows the VCC12 until it reaches its regulation point

at ~5.8V. Both VCC and VCC12 must be past their rising

POR trip points before SS1 starts rising. The order doesn’t

matter, and may be different, especially when the VCC uses

an independent supply. In most cases with the shunt

regulator, the VCC12 POR is 2nd; when it hits ~8V, the

SS1/EN1 ramp begins. When SS1/EN1 reaches ~1V, the

output starts ramping up, and the ramp is complete when

SS1/EN1 reaches ~3.3V.

Note that if VIN1 is tied to a supply other than either VCC or

VCC12, then it MUST be up above the desired output

voltage (or at least ramping there ahead of the output)

before the SS1/EN1 reaches ~1V. If not, the short-circuit

protection will trigger, and shut down all three outputs,

requiring a POR on either VCC or VCC12 to restart. If either

VCC or VCC12 is used as VIN, then the voltage levels

should be sufficient, as long as the design can function at the

POR levels, since both must hit their POR levels before

starting up. So, for example, if the VCC12 supply was also

used as VIN, then as long as the output could start up at

VIN = ~8V (the VCC12 rising POR trip point) the start-up

condition is satisfied.

PGOOD

The PGOOD open-drain pull-down device is on when power

is first applied to the IC, forcing the pin to a logic low, for

power “Not Good”. After all 3 soft-start pins complete their

ramp up with no faults (no short detected on either switcher),

the power is considered “Good”, and the output pin goes

high-impedance (to be pulled up to a logic high level with an

external pull-up resistor). Figure 10 shows an example, with

a fast SS1 and VOUT1, a slower SS3 and VOUT3, and the

PGOOD output. The PGOOD waits for the last of the SS

signals (EN3/SS3 here) to reach their ramp-done trip point

before it goes high.

If any of the SS/EN pins is held low, PGOOD will not go high;

thus, if one of the three outputs is not used, and the PGOOD

function is desired, then that SS/EN should be allowed to

charge high, and the other pins of the unused regulator

should be tied so as not to cause a fault or shutdown.

Options for OUT1 include: tying FB1 to COMP1, or tying FB1

to VCC, and leaving COMP1 open. VOUT2 is a little more

difficult; Tie REFIN, FB2, COMP2 to GND; or tie FB2 to

COMP2, and tie REFIN to a voltage well under 3V (to avoid

the short-circuit shutdown). In all of these cases, leave the

LGATE and UGATE pins open; tie BOOT pin to VCC12. See

section “Linear (VOUT3) Component Selection” for

considerations for disabling the linear output, while keeping

PGOOD active.

FIGURE 9. START-UP (12V, VCC, SS1/EN1, VOUT1)

SS1/EN1

SS2/EN2

SS3/EN3

CSS1

CSS2

CSS3

EN3

EN1, 2

OPEN-DRAIN

LOGIC SIGNALS

FIGURE 8. 1 AND 2 ENABLED TOGETHER BUT HAVE

INDEPENDENT SOFT-STARTS. 3 IS FULLY

INDEPENDENT.

GND>

VOUT1 (1V/DIV)

12V (4V/DIV)

GND>

SS1/EN1 (1V/DIV)

VCC (4V/DIV)

~8V POR

~1.0V

~3.3V

FIGURE 10. PGOOD OUTPUT

GND>

SS1/EN1 (1V/DIV)

SS3/EN3 (1V/DIV)

GND>

VOUT3 (1V/DIV)

VOUT1 (1V/DIV)

PGOOD (1V/DIV)

GND>

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