XRT83SL314IB datasheet(70/85 Pages) EXAR

70 / 85 page

XRT83SL314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

REV. P1.0.5

PRELIMINARY

TABLE 44: MICROPROCESSOR REGISTER 0XE3H BIT DESCRIPTION

RxTCNTL

Receive Termination Select Control

This bit sets the LIU to control the RxTSEL function with either the

individual channel register bit or the global hardware pin.

0 = Control of the receive termination is set to the register bits

1 = Control of the receive termination is set to the hardware pin

R/W

EQFLAG5

EQFLAG4

EQFLAG3

EQFLAG2

EQFLAG1

EQFLAG0

Equalizer Attenuation Flag

EQFLAG[5:0] is used to generate an interrupt condition for an

RLOS other than the default setting described in the datasheet. A

desired value can be programmed into this register. If EQFLAGE

is enabled in register 0x04h and if this 6-Bit binary word is equal to

the 6-Bit cable loss indicator, an interrupt will be generated.

R/W

GLOBAL REGISTER (0XE3H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

Reserved

This Register Bit is Not Used

R/W

Reserved

This Register Bit is Not Used

R/W

Reserved

This Register Bit is Not Used

R/W

Reserved

This Register Bit is Not Used

R/W

SL1

SL0

Slicer Level Select

00 = 50%

01 = 45%

10 = 55%

11 = 68%

R/W

EQG1

EQG0

Equalizer Gain Control

00 = Normal

01 = Reduce Gain by 1dB

10 = Reduce Gain by 3dB

11 = Normal

R/W

GLOBAL REGISTER (0XE2H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

XRT83SL314IB Datasheet(PDF) 70 Page - Exar Corporation

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