ISL6567 datasheet(20/26 Pages) RENESAS

20 / 26 page

ISL6567

FN9243 Rev 4.00

Page 20 of 26

August 9, 2011

peak dependent on the quality factor (Q) of the output filter,

which is not shown. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

compensation gain at FP2 against the capabilities of the error

amplifier. The closed loop gain, GCL, is constructed on the

log-log graph of Figure 25 by adding the modulator gain, GMOD

(in dB), to the feedback compensation gain, GFB (in dB). This is

equivalent to multiplying the modulator transfer function and

the compensation transfer function and then plotting the

resulting gain. A stable control loop has a gain crossing with close

to a -20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin. The mathematical model presented makes a

number of approximations and is generally not accurate at

frequencies approaching or exceeding half the switching

frequency. When designing compensation networks, select target

crossover frequencies in the range of 10% to 30% of the per-

channel switching frequency, FSW.

OUTPUT FILTER DESIGN

The output inductors and the output capacitor bank together

form a low-pass filter responsible for smoothing the square

wave voltage at the phase nodes. Additionally, the output

capacitors must also provide the energy required by a fast

transient load during the short interval of time required by the

controller and power train to respond. Because it has a low

bandwidth compared to the switching frequency, the output

filter limits the system transient response leaving the output

capacitor bank to supply the load current or sink the inductor

currents, all while the current in the output inductors increases

or decreases to meet the load demand.

In high-speed converters, the output capacitor bank is

amongst the costlier (and often the physically largest) parts of

the circuit. Output filter design begins with consideration of the

critical load parameters: maximum size of the load step,

I,

the load-current slew rate, di/dt, and the maximum allowable

output voltage deviation under transient loading,

VMAX.

Capacitors are characterized according to their capacitance,

ESR, and ESL (equivalent series inductance).

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the voltage

drop across the ESR increases linearly until the load current

reaches its final value. The capacitors selected must have

sufficiently low ESL and ESR so that the total output voltage

deviation is less than the allowable maximum. Neglecting the

contribution of inductor current and regulator response, the

output voltage initially deviates according to Equation 21.

The filter capacitor must have sufficiently low ESL and ESR so

that

V < VMAX.

Most capacitor solutions rely on a mixture of high-frequency

capacitors with relatively low capacitance in combination with

bulk capacitors having high capacitance but limited high-

frequency performance. Minimizing the ESL of the high-

frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

The ESR of the bulk capacitors is also responsible for the

majority of the output-voltage ripple. As the bulk capacitors

sink and source the inductor AC ripple current, a voltage

develops across the bulk-capacitor ESR equal to IPP. Thus,

once the output capacitors are selected and a maximum

allowable ripple voltage, VPP(MAX), is determined from an

analysis of the available output voltage budget, Equation 22

can be used to determine a lower limit on the output

inductance.

Since the capacitors are supplying a decreasing portion of the

load current while the regulator recovers from the transient,

the capacitor voltage becomes slightly depleted. The output

inductors must be capable of assuming the entire load current

before the output voltage decreases more than

VMAX. This

places an upper limit on inductance.

While Equation 23 addresses the leading edge, Equation 24

gives the upper limit on L for cases where the trailing edge of

the current transient causes a greater output voltage deviation

than the leading edge.

Normally, the trailing edge dictates the selection of L, if the

duty cycle is less than 50%. Nevertheless, both inequalities

should be evaluated, and L should be selected based on the

lower of the two results. In all equations in this paragraph, L is

the per-channel inductance and C is the total output bulk

capacitance.

FP1

FZ2

OPEN LOOP E/A GAIN

FZ1

FP2

FLC

FCE

COMPENSATION GAIN

FREQUENCY

MODULATOR GAIN

FIGURE 25. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP GAIN

dMAX V



VOSC

--------------------------------

log

--------





log

LOG

GMOD

GFB

GCL

VESL

 di

-----

ESR

 I



(EQ. 21)

LESR

VIN 2VOUT



–

 VOUT



fS VIN VPP MAX





----------------------------------------------------------





(EQ. 22)

4CVOUT



I



-----------------------------

VMAX IESR



–







(EQ. 23)

2.5 C



I



----------------

V

MAX

IESR



–

 V

–







(EQ. 24)

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