EL7586ILZ datasheet(13/21 Pages) RENESAS

13 / 21 page

EL7586, EL7586A

FN9210 Rev 2.00

Page 13 of 21

January 17, 2006

Operation of the DELB Output Function

An open drain DELB output is provided to allow the boost

output voltage, developed at C2 (see application diagram),

to be delayed via an external switch (Q4) to a time after the

VBOOST supply and negative VOFF charge pump supply

have achieved regulation during the start-up sequence

shown in Figures 33 and 34. This then allows the AVDD and

VON supplies to start-up from 0V instead of the normal offset

voltage of VIN-VDIODE (D1) if Q4 were not present.

When DELB is activated by the start-up sequencer, it sinks

50µA allowing a controlled turn-on of Q4 and charge-up of

C9. C16 can be used to control the turn-on time of Q4 to

reduce inrush current into C9. The potential divider formed

by R9 and R8 can be used to limit the VGS voltage of Q4 if

required by the voltage rating of this device. When the

voltage at DELB falls to less than 0.6V, the sink current is

increased to ~1.2mA to firmly pull DELB to 0V.

The voltage at DELB is monitored by the fault protection

circuit so that if the initial 50µA sink current fails to pull DELB

below ~0.6V after the start-up sequencing has completed,

then a fault condition will be detected and a fault time-out

ramp will be initiated on the CDEL capacitor (C7).

Operation of the PG Output Function

The PG output consists of an internal pull-up PMOS device to

VIN, to turn-off the external Q1 protection switch and a current

limited pull-down NMOS device which sinks ~15µA allowing a

controlled turn-on of Q1 gate capacitance. CO is used to

control how fast Q1 turns-on - limiting inrush current into C1.

When the voltage at the PG pin falls to less than 0.6V, the PG

sink current is increased to ~1.2mA to firmly pull the pin to 0V.

The voltage at PG is monitored by the fault protection circuit

so that if the initial 15µA sink current fails to pull PG below

~0.6V after the start-up sequencing has completed, then a

fault condition will be detected and a fault time-out ramp will

be initiated on the CDEL capacitor (C7).

Cascaded MOSFET Application

A 20V N-channel MOSFET is integrated in the boost

regulator. For the applications where the output voltage is

greater than 20V, an external cascaded MOSFET is needed

as shown in Figure 27. The voltage rating of the external

MOSFET should be greater than VBOOST.

Linear-Regulator Controllers (VON, VLOGIC, and

VOFF)

The EL7586 and EL7586A include three independent linear-

regulator controllers, in which two are positive output voltage

(VON and VLOGIC), and one is negative. The VON, VOFF,

and VLOGIC linear-regulator controller functional diagrams,

applications circuits are shown in Figures 28, 29, and 30

respectively.

Calculation of the Linear Regulator Base-Emitter

Resistors (RBL, RBP and RBN)

For the pass transistor of the linear regulator, low frequency

gain (Hfe) and unity gain freq. (fT) are usually specified in the

datasheet. The pass transistor adds a pole to the loop

transfer function at fp =fT/Hfe. Therefore, in order to

maintain phase margin at low frequency, the best choice for

a pass device is often a high frequency low gain switching

transistor. Further improvement can be obtained by adding a

base-emitter resistor RBE (RBP, RBL, RBN in the Functional

Block Diagram), which increase the pole frequency to:

fp =fT*(1+ Hfe *re/RBE)/Hfe, where re = KT/qIc. So choose

the lowest value RBE in the design as long as there is still

enough base current (IB) to support the maximum output

current (IC).

We will take as an example the VLOGIC linear regulator. If a

Fairchild FMMT549 PNP transistor is used as the external

pass transistor, Q5 in the application diagram, then for a

maximum VLOGIC operating requirement of 500mA the data

sheet indicates Hfe_min = 100.

The base-emitter saturation voltage is: Vbe_max = 1.25V

(note this is normally a Vbe ~ 0.7V, however, for the Q5

transistor an internal Darlington arrangement is used to

increase it's current gain, giving a 'base-emitter' voltage of

2xVBE).

(Note that using a high current Darlington PNP transistor for

Q5 requires that VIN > VLOGIC + 2V. Should a lower input

voltage be required, then an ordinary high gain PNP

transistor should be selected for Q5 so as to allow a lower

collector-emitter saturation voltage).

EL7586

EL7586A

VBOOST

VIN

FIGURE 27. CASCADED MOSFET TOPOLOGY FOR HIGH

OUTPUT VOLTAGE APPLICATIONS

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