ISL88731CEVAL2Z datasheet(21/26 Pages) RENESAS

21 / 26 page

ISL88731C

FN6978 Rev 3.00

Page 21 of 26

June 8, 2011

charger output. Figure 25 shows the adapter current limit control

loop.

The loop response equations, bode plots and the selection of

CICOMP are the same as the charge current control loop with loop

gain reduced by the duty cycle and the ratio of RS1/RS2. In other

words, if RS1 = RS2 and the duty cycle D = 50%, the loop gain will

be 6dB lower than the loop gain in Figure 25. This gives lower

crossover frequency and higher phase margin in this mode. If

RS1/RS2 = 2 and the duty cycle is 50% then the adapter current

loop gain will be identical to the gain in Figure 25.

A filter should be added between RS1 and CSIP and CSIN to reduce

switching noise. The filter roll off frequency should be between the

cross over frequency and the switching frequency (~100kHz).

Voltage Control Loop

When the battery is charged to the voltage set by ChargeVoltage

output (assuming that the adapter current is below the limit set

by ACLIM). The voltage error amplifier (GMV) discharges the cap

on VCOMP to limit the output voltage. The current to the battery

decreases as the cells charge to the fixed voltage and the voltage

across the internal battery resistance decreases. As battery

current decreases the 2 current error amplifiers (GMI and GMS)

output their maximum current and charge the capacitor on

ICOMP to its maximum voltage (limited to 0.3V above VCOMP).

With high voltage on ICOMP, the minimum voltage buffer output

equals the voltage on VCOMP.

The voltage control loop is shown in Figure 26.

Output LC Filter Transfer Functions

The gain from the phase node to the system output and battery

depend entirely on external components. Typical output LC filter

response is shown in Figure 27. Transfer function ALC(s) is shown

in Equation 22:

The resistance RO is a combination of MOSFET rDS(ON), inductor

DCR, RSENSE and the internal resistance of the battery (normally

between 50m

 and 200m) The worst case for voltage mode

control is when the battery is absent. This results in the highest Q

of the LC filter and the lowest phase margin.

The compensation network consists of the voltage error amplifier

GMV and the compensation network RVCOMP, CVCOMP which give

the loop very high DC gain, a very low frequency pole and a zero

at FZERO1. Inductor current information is added to the feedback

to create a second zero FZERO2. The low pass filter RF2, CF2

between RS2 and ISL88731C add a pole at FFILTER. R3 and R4

are internal divider resistors that set the DC output voltage. For a

3-cell battery, R3 = 500k and R4 = 100k. The following

equations relate the compensation network’s poles, zeros and

FIGURE 24. CHARGE CURRENT LOOP BODE PLOTS

-60

-40

-20

0.01k

0.1k

10k

100k

FREQUENCY (Hz)

COMPENSATOR

MODULATOR

LOOP

FPOLE2

FFILTER

FPOLE1

FZERO

CICOMP

RBAT

ICOMP

PHASE

0.25

DACS

GMS

RS1

DCIN

CSSN

CA1

CSSP

CF1

RF1

RS2

CSON

20X

CSOP

CF2

RF2

RESR

RFET_RDSON

RL_DCR

CA2

FIGURE 25. ADAPTER CURRENT LIMIT LOOP



FIGURE 26. VOLTAGE CONTROL LOOP

VCOMP

CSON

PHASE

CSOP

0.25

GMV

CVCOMP

RVCOMP

DACV

20x

RS2

RBAT

RESR

CF2

RF2

RFET_RDSON

RL_DCR

CA2



ALC

ESR

--------------

–







-----------



LC Q





----------------------- 1







---------------------------------------------------------

ESR

RESR Co





-----------------------------



LCo





-----------------------

QRo

------



(EQ. 22)

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