EL8302 datasheet(11/14 Pages) RENESAS

11 / 14 page

EL8302

FN7348 Rev 2.00

Page 11 of 14

May 6, 2005

a negative going pulse, we can chop it off. Figure 31 shows a

gain of 2 connections for EL8302. Figure 32 shows the

complete input video signal applied at the input, as well as the

output signal with the negative going sync pulse removed.

MULTIPLEXER

Besides the normal power down usage, the ENABLE pin of the

EL8302 can be used for multiplexing applications. Figure 33

shows two channels with the outputs tied together, driving a

back terminated 75

 video load. A 2VP-P 2MHz sine wave is

applied to Amp A and a 1VP-P 2MHz sine wave is applied to

Amp B. Figure 34 shows the ENABLE signal and the resulting

output waveform at VOUT. Observe the break-before-make

operation of the multiplexing. Amp A is on and VIN1 is passed

through to the output when the ENABLE signal is low and turns

off in about 25ns when the ENABLE signal is high. About

200ns later, Amp B turns on and VIN2 is passed through to the

output. The break-before-make operation ensures that more

than one amplifier isn’t trying to drive the bus at the same time.

SINGLE SUPPLY VIDEO LINE DRIVER

The EL8302 is wideband rail-to-rail output op amplifiers with

large output current, excellent dG, dP, and low distortion that

allow them to drive video signals in low supply applications.

Figure 35 is the single supply non-inverting video line driver

configuration and Figure 36 is the inverting video ling driver

configuration. The signal is AC coupled by C1. R1 and R2 are

used to level shift the input and output to provide the largest

output swing. RF and RG set the AC gain. C2 isolates the

virtual ground potential. RT and R3 are the termination

resistors for the line. C1, C2 and C3 are selected big enough to

minimize the droop of the luminance signal.

FIGURE 31. SYNC PULSE REMOVER

VOUT

VIN



VS+

VS-

FIGURE 32. VIDEO SIGNAL

0.5V

M = 10µs/DIV

VOUT

VIN

FIGURE 33. TWO TO ONE MULTIPLEXER

+2.5V

2MHz



-2.5V

VOUT



1VP-P

+2.5V

2MHz



-2.5V

2VP-P

ENABLE

FIGURE 34.

-0.5V

-1.5V

-2.5V

M = 50ns/DIV

ENABLE

-1V

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