7 / 15 page
CY7C09159
CY7C09169
PRELIMINARY
7
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)
[5,6,7,8]
Read Cycle for Pipelined Operation (FT/PIPE = VIH)
[5,6,7,8]
Notes:
5.
OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
6.
ADS = VIL, CNTEN and CNTRST = VIH.
7.
The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
8.
Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
tCH1
tCL1
tCYC1
tSC
tHC
tDC
tOHZ
tOE
tSC
tHC
tSW
tHW
tSA
tHA
tCD1
tCKHZ
tDC
tOLZ
tCKLZ
An
An+1
An+2
An+3
Qn
Qn+1
Qn+2
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
tCH2
tCL2
tCYC2
tSC
tHC
tSW
tHW
tSA
tHA
An
An+1
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
An+2
An+3
tSC
tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
Qn
Qn+1
Qn+2
1 Latency
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
