IMX6SLLCEC datasheet(23/90 Pages) NXP

23 / 90 page

Electrical Characteristics

i.MX 6SLL Applications Processors for Consumer Products, Rev. 0.2, 11/2017

NXP Semiconductors

NOTE

The currents on the VDD_HIGH_CAP and VDD_USB_CAP were

identified to be the voltage divider circuits in the USB-specific level

shifters.

4.2

Power Supplies Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

•

Excessive current during power-up phase

•

Prevention of the device from booting

•

Irreversible damage to the processor (worst-case scenario)

4.2.1

Power-Up Sequence

For power-up sequence, the restrictions are as follows:

•

VDD_SNVS_IN supply must be turned ON before any other power supply. It may be connected

(shorted) with VDD_HIGH_IN supply.

•

If a coin cell is used to power VDD_SNVS_IN, then ensure it is connected before any other supply

is switched on.

•

VDD_SOC_IN must be turned on before any other digital IO power supply.

•

POR_B signal must be immediately asserted at power-up and remain asserted after the last power

rail reaches its working voltage.

•

VDD_ARM_IN may be applied with no restrictions.

•

NVCC33_IO must be applied before NVCC18_IO.

NOTE

See the i.MX 6SLL Reference Manual (IMX6SLLRM) for further details

and to ensure that all necessary requirements are being met.

NOTE

Ensure that there is no back voltage (leakage) from any supply on the board

towards the 3.3 V supply (for example, from the external components that

use both the 1.8 V and 3.3 V supplies).

NOTE

USB_OTG1_VBUS and USB_OTG2_VBUS are not part of the power

supply sequence and can be powered at any time.

Table 13. USB PHY Current Consumption in Power Down Mode

VDD_USB_CAP (3.0 V)

VDDHIGH_CAP (2.5 V)

NVCC_PLL (1.1 V)

Current

5.1

A1.7 A

<0.5

A

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