AD5748 datasheet(30/32 Pages) AD

30 / 32 page

AD5748

Data Sheet

Rev. B | Page 30 of 32

APPLICATIONS INFORMATION

TRANSIENT VOLTAGE PROTECTION

The AD5748 contains ESD protection diodes that prevent damage

from normal handling. The industrial control environment can,

however, subject I/O circuits to much higher transients. To protect

the AD5748 from excessively high voltage transients, external

power diodes and a surge current limiting resistor may be

required, as shown in Figure 54. The constraint on the resistor

value is that, during normal operation, the output level at IOUT

must remain within its voltage compliance limit of AVDD − 2.75 V,

and the two protection diodes and resistor must have appropri-

ate power ratings. Further protection can be added with transient

voltage suppressors if needed.

IOUT

AVDD

AVSS

AD5748

RLOAD

Figure 54. Output Transient Voltage Protection

THERMAL CONSIDERATIONS

It is important to understand the effects of power dissipation

on the package and on junction temperature. The internal junction

temperature should not exceed 125°C. The AD5748 is packaged

in a 32-lead LFCSP 5, 5 mm × 5 mm package. The thermal

impedance, θJA, is 42°C/W. It is important that the devices are

not operated under conditions that cause the junction tempera-

ture to exceed its junction temperature.

Worst-case conditions occur when the AD5748 is operated from

the maximum AVDD (26.4 V) while driving the maximum

current (24 mA) directly to ground. The quiescent current of the

AD5748 should also be taken into account, nominally ~4 mA.

The following calculations estimate maximum power dissipation

under these worst-case conditions, and determine maximum

ambient temperature based on the power dissipation:

Power Dissipation = 26.4 V × 28 mA = 0.7392 W

Temp Increase = 42°C × 0.7392 W = 31°C

Maximum Ambient Temp = 125°C − 31°C = 94°C

These figures assume that proper layout and grounding

techniques are followed to minimize power dissipation,

as outlined in the Layout Guidelines section.

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The PCB on which the AD5748 is

mounted should be designed so that the AD5748 lies on the

analog plane.

The AD5748 should have ample supply bypassing of 10 μF

in parallel with 0.1 μF on each supply located as close to the

package as possible, ideally right up against the device. The

10 μF capacitors are the tantalum bead type. The 0.1 μF capaci-

tor should have low effective series resistance (ESR) and low

effective series inductance (ESI) such as the common ceramic

types, which provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

In systems where there are many devices on one board, it is often

useful to provide some heat sinking capability to allow the power

to dissipate easily.

AD5748

AVSS

PLANE

BOARD

Figure 55. Paddle Connection to Board

The AD5748 has an exposed paddle beneath the device. This

paddle is connected to the AVSS supply for the part. For opti-

mum performance, special considerations should be used to

design the motherboard and to mount the package. For enhanced

thermal, electrical, and board level performance, the exposed

paddle on the bottom of the package is soldered to the correspond-

ing thermal land paddle on the PCB. Thermal vias are designed

into the PCB land paddle area to further improve heat dissipation.

The AVSS plane on the device can be increased (as shown in

Figure 55) to provide a natural heat sinking effect.

AD5748 Datasheet(PDF) 30 Page - Analog Devices

AD5748 Datasheet(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL