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X9259 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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X9259 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 21 page  FN8169 Rev 6.00 Page 1 of 21 December 12, 2014 FN8169 Rev 6.00 December 12, 2014 X9259 Single Supply/Low Power/256-Tap/2-Wire Bus Quad Digitally-Controlled (XDCP™) Potentiometers DATASHEET The X9259 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Four separate potentiometers in one package • 256 resistor taps–0.4% resolution • 2-wire serial interface for write, read, and transfer operations of the potentiometer • Wiper resistance: 100Ω typical at VCC = 5V • 4 nonvolatile data registers for each potentiometer • Nonvolatile storage of multiple wiper positions • Standby current <5µA max •VCC: 2.7V to 5.5V operation • 50kΩ version of total resistance • Endurance: 100,000 data changes per bit per register • 100 year data retention • Single supply version of X9258 • 24 Ld SOIC, 24 Ld TSSOP •Low power CMOS • Pb-Free (RoHS compliant) Functional Diagram POWER UP, INTERFACE CONTROL AND VCC VSS 2-WIRE RH0 RL0 DCP0 RW0 A1 SDA SCL A3 A2 WP WCR0 DR00 DR01 DR02 DR03 RH1 RL1 DCP1 RW1 WCR1 DR10 DR11 DR12 DR13 RH2 RL2 DCP2 RW2 WCR2 DR20 DR21 DR22 DR23 RH3 RL3 DCP3 RW3 WCR3 DR30 DR31 DR32 DR33 A0 INTERFACE STATUS |
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