AD8106ASTZ datasheet(5/22 Pages) AD

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Data Sheet

AD8106/AD8107

Rev. A | Page 5 of 22

TIMING CHARACTERISTICS

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

ns min

Data setup time

100

ns min

CLK pulse width

ns min

Data hold time

100

ns min

CLK pulse separation

ns min

CLK to UPDATE delay

ns min

UPDATE pulse width

–

ns max

Propagation delay, UPDATE to switch on or off

–

100

ns max

CLK, UPDATE rise and fall times

–

200

ns min

RESET time

1 = LATCHED

CLK

D0 TO D4

A0 TO A2

0 = TRANSPARENT

UPDATE

Figure 2. Timing Diagram

Table 3. Logic Levels

VIH

VIL

IIH

IIL

RESET, CLK, D0, D1, D2, D3, D4,

A0, A1, A2, CE, UPDATE

RESET, CLK, D0, D1, D2, D3, D4,

A0, A1, A2, CE, UPDATE

RESET, CLK, D0, D1, D2, D3, D4,

A0, A1, A2, CE, UPDATE

RESET, CLK, D0, D1, D2, D3, D4,

A0, A1, A2, CE, UPDATE

2.0 V min

0.8 V max

20 µA max

−400 µA min

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