AD8178 datasheet(29/37 Pages) AD

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Data Sheet

AD8178

Rev. A | Page 29 of 37

In similar fashion, if UPDATE is taken low after initial power-up,

the random power-up data in the shift register is programmed into

the matrix. Therefore, to prevent the crosspoint from being

programmed into an unknown state, do not apply a logic level

to UPDATE after power is initially applied. Programming the

device into a known state after reset or power-up is a one-time

event that is accomplished by the following two steps:

Output 4 to Output 0 are programmed to the off state

while holding the CLR input at a logic high.

Each output (Output 4 to Output 0) is programmed to its

desired state while holding the CLR input at a logic low.

CLR is held at logic low thereafter.

To change the programming of an output via parallel

programming, take CS low, and take SER/PAR and UPDATE

high. Leave the serial programming clock, CLK, high during

parallel programming. Start the parallel clock, WE, in the high

state. Put the 3-bit address of the output to be programmed on

A2 to A0. Data Bit D3 to Data Bit D0 must contain the information

that identifies the input that is programmed to the output that is

addressed. Data Bit D4 determines the enabled state of the output.

If D4 is low (output disabled), the data on D3 to D0 does not

matter.

After the desired address and data signals have been established,

they can be latched into the shift register by a high-to-low transi-

tion of the WE signal. The matrix is not programmed, however,

until the UPDATE signal is taken low. It is thus possible to latch

in new data for several or all of the outputs first via successive

negative transitions of WE while UPDATE is held high, and then

have all the new data take effect when UPDATE goes low. Use

this technique to program the device for the first time after power-

up when using parallel programming.

Programming the device to a known state can be accomplished

in serial programming mode by clocking in the entire 45-bit

sequence immediately after reset or power-up.

Reset

When powering up the AD8178, it is usually desirable to have

the outputs come up in the disabled state. The RST pin, when

taken low, causes all outputs to be in the disabled state. However,

the RST signal does not reset all registers in the AD8178. This is

important when operating in the parallel programming mode.

See the Parallel Programming Description section for information

about programming internal registers after power-up. Serial

programming programs the entire matrix each time, so no

special considerations apply.

Because the data in the shift register is random after power-up,

do not use it to program the matrix, or the matrix can enter

unknown states. To prevent this, do not apply a logic low signal

to UPDATE initially after power-up. First load the shift register

with the desired data, and only then can the UPDATE be taken

low to program the device.

The RST pin has a 20 kΩ pull-up resistor to VDD that can be

used to create a simple power-up reset circuit. A capacitor from

RST to ground holds RST low for some time, while the rest of the

device stabilizes. The low condition causes all the outputs to be

disabled. The capacitor then charges through the pull-up resistor

to the high state, thus allowing full programming capability of

the device.

DIFFERENTIAL AND SINGLE-ENDED OPERATION

Although the AD8178 has fully differential inputs and outputs,

it can also operate in single-ended fashion. Single-ended and

differential configurations are discussed in the following

sections, along with implications on gain, impedances, and

terminations.

Differential Input

Each differential input to the AD8178 is applied to a differential

receiver. These receivers allow the user to drive the inputs with

an uncertain common-mode voltage, such as from a remote source

over twisted pair. The receivers respond only to the differences

in input voltages and restore an internal common mode suitable

for the internal signal path. Noise or crosstalk, which affect each

the inputs of each receiver equally, are rejected by the input stage,

as specified by its common-mode rejection ratio (CMRR).

Furthermore, the overall common-mode voltage of all three

differential pairs comprising an RGB channel is processed and

rejected by a separate circuit block. For example, a static discharge

or a resistive voltage drop in a middle-of-Cat-5-run application

with sync-on CM signaling coupling into all three pairs in an RGB

channel are rejected at the output of the AD8178, while the

sync-on CM signals are allowed through the switch.

The circuit configuration used by the differential input receivers

is similar to that of several Analog Devices, Inc. general-purpose

differential amplifiers, such as the AD8131. The topology is that

of a voltage-feedback amplifier with internal gain resistors. The

input differential impedance for each receiver is 5 kΩ in parallel

with 10 kΩ or 3.33 kΩ, as shown in Figure 49.

IN+

IN–

RCM

OUT–

OUT+

TO SWITCH MATRIX

RCVR

Figure 49. Input Receiver Equivalent Circuit

This impedance creates a small differential termination error if

the user does not account for the 3.33 kΩ parallel element.

However, this error is less than 1% in most cases. Additionally,

the source impedance driving the AD8178 appears in parallel

with the internal gain-setting resistors, such that there may be a

gain error for some values of source resistance.

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