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HMC628LP4 Datasheet(PDF) 8 Page - Analog Devices |
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HMC628LP4 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 14 page ![]() 12 - 41 For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 12 Serial Control Interface Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) The HMC628LP4(E) contains a 3-wire SPI compatible digital interface (DATA, CLK, LE). It is activated when P/S is kept high. The 5-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. Standard logic families work well. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, 5-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. When P/S is low, 3-wire SPI interface inputs (DATA, CLK, LE) are disabled and serial input register is loaded asynchronously with parallel digital inputs (B0-B4). When Le is high, 5-bit parallel data is transferred to the attenuator. For all modes of operations, attenuation state will stay constant while LE is kept low. Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. Timing Diagram (Latched Parallel Mode) HMC628LP4 / 628LP4E v07.0410 BiCMOS MMIC 5-Bit DIGITAL VARIABLE GAIN AMPLIFIER, 50 - 800 MHz Parameter Typ. Min. serial period, t SCK 100 ns Control set-up time, t CS 20 ns Control hold-time, t CH 20 ns LE Set up-time, t LN 10 ns Min. LE pulse width, t LEW 10 ns Min LE pulse spacing, t LES 530 ns Serial clock hold-time from LE, t CKN 10 ns Hold Time, t PH 0 ns Latch Enable Minimum Width, t LEN 10 ns Setup Time, t PS 2 ns Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com Application Support: Phone: 1-800-ANALOG-D |
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