Input Acquisition and Settling

Clocking in a control byte starts input acquisition. The

main capacitor array starts acquiring the input as soon

as a start bit is recognized, using the same input range

as the previous conversion. If the opposite input range

is selected by the second DIN bit, the part immediately

switches to the new sampling mode. Acquisition time is

one-and-a-half clock cycles shorter when switching

from unipolar to bipolar or bipolar to unipolar modes

than when continuously converting in the same mode.

Acquisition can be extended by eight clock cycles by

setting M1 = 1 and M0 = 1 (long acquisition mode). The

sampling instant in short acquisition completes on the

falling edge of the sixth clock cycle after the start bit

(Figure 2). Acquisition is 5 clock cycles in short acquisi-

tion mode and 13 clock cycles in long acquisition

mode. Short acquisition mode is 24 clock cycles per

conversion. Using the external clock to run the conver-

sion process limits unipolar conversion speed to

125ksps instead of 150ksps as in bipolar mode. The

input resistance in unipolar mode is larger than that of

bipolar mode (Figure 1). The RC time constant in unipo-

lar mode is larger than that of bipolar mode, reducing

the maximum conversion rate in 24 external clock

mode. Long acquisition mode with external clock

allows both unipolar and bipolar sampling of 112ksps

as (3.6MHz / 32 clock cycles) by adding eight extra

clock cycles to the conversion.

Most applications require an input buffer amplifier. If

the input signal is multiplexed, the input channel should

be switched immediately after acquisition, rather than

near the end of or after a conversion. This allows more

time for the input buffer amplifier to respond to a large

step change in input signal. The input amplifier must

have a high enough slew rate to complete the required

output voltage change before the beginning of the

acquisition time.

At the beginning of acquisition, the capacitive DAC is

connected to the amplifier output, causing some output

disturbance. Ensure that the sampled voltage has set-

tled to within the required limits before the end of the

acquisition time. If the frequency of interest is low, AIN

can be bypassed with a large enough capacitor to

charge the capacitive DAC with very little change in

voltage. However, for AC use, AIN must be driven by a

wideband buffer (at least 10MHz), which must be sta-

ble with the DAC’s capacitive load (in parallel with any

AIN bypass capacitor used) and also must settle quickly

(Figure 7).

Digital Noise

Digital noise can couple to AIN and REF. The conver-

sion clock (SCLK) and other digital signals that are

active during input acquisition contribute noise to the

conversion result. If the noise signal is synchronous to

the sampling interval, an effective input offset is pro-

duced. Asynchronous signals produce random noise

on the input, whose high-frequency components may

be aliased into the frequency band of interest. Minimize

noise by presenting a low impedance (at the frequen-

cies contained in the noise signal) at the inputs. This

requires bypassing AIN to AGND, or buffering the input

with an amplifier that has a small-signal bandwidth of

several MHz, or preferably both. AIN has a bandwidth

of about 4MHz.

Offsets resulting from synchronous noise (such as the

conversion clock) are canceled by the MAX1144/

MAX1145’s calibration scheme. However, because the

14-Bit ADCs, 150ksps, 3.3V Single Supply

______________________________________________________________________________________

13

4

7

6

2

3

IN

0.0033

µF

0.1

µF

0.1

µF

100pF

1k

Ω

1k

Ω

AIN

Figure 7. AIN Buffer for AC/DC Use