IR3086

Page 14 of 15

9/1/03

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

•

Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND)

and power ground plane (PGND).

•

Connect PGND to LGND pins of each phase IC to the ground tab under it.

•

In order to reduce the noise coupled to SCOMP pin of phase ICs, use a dedicated wire to connect the

capacitor CSCOMP to LGND pin, but connect PWM ramp capacitor CPWMRMP, phase delay

programming resistor RRAMP2, decoupling capacitor CVCC to LGND plane through vias.

•

Connect the decoupling capacitor low side gate driver CVCCL and the ground tab under the phase IC to

PGND plane through vias.

•

Place the decoupling capacitor CVCC as close as possible to VCC pin of the control IC, and place the

decoupling capacitors CVCC and CVCCL as close as possible to VCC and VCCL pins of the phase IC

respectively.

•

Bus signals should not cross over the fast transition nodes, such as switching nodes and gate drive

output.

•

Use Kelvin connections for the current sense signals, and use the ground plane to shield the current

sense traces.

•

Place the phase ICs as close as possible to the MOSFETs to reduce the parasitic resistance and

inductance of the gate drive paths.

•

Place the input capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Replace

the bigger-package ceramic capacitors with multiple smaller-package ones to reduce the parasitic

inductance.

•

There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor,

output capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and

the load. Route the switching power paths using wide and short traces or polygons; use multiple vias for

connections between layers.

Figure 8 - Layout of Phase IC Components

LGND

VCC

SCOMP

CSIN+

CSIN-

DACIN

BIASIN

To Signal Bus

To Inductor

Current Sensing

To PGND

Plane

To LGND

Plane

To VIN

To LGND

Plane

To Gate Drive

Voltage

PHSFLT or OPTIPHS

EAIN

PWMRMP

To MOSFETs

To LGND Plane

PGND PLANE

LGND PLANE

To

Switching

Node

LGND

VCC

SCOMP

CSIN+

CSIN-

DACIN

BIASIN

To Signal Bus

To Inductor

Current Sensing

To PGND

Plane

To LGND

Plane

To VIN

To LGND

Plane

To Gate Drive

Voltage

PHSFLT or OPTIPHS

EAIN

PWMRMP

To MOSFETs

To LGND Plane

PGND PLANE

LGND PLANE

To

Switching

Node